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Re: [Qemu-arm] [PATCH v2 06/13] hw/misc/tz-mpc.c: Implement registers
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH v2 06/13] hw/misc/tz-mpc.c: Implement registers |
Date: |
Fri, 15 Jun 2018 10:04:25 +0100 |
On 14 June 2018 at 21:36, Auger Eric <address@hidden> wrote:
> Hi Peter,
>
> On 06/04/2018 05:29 PM, Peter Maydell wrote:
>> Implement the missing registers for the TZ MPC.
>>
>> Signed-off-by: Peter Maydell <address@hidden>
>> + case A_INT_CLEAR:
>> + if (value & R_INT_CLEAR_IRQ_MASK) {
>> + s->int_stat = 0;
>> + tz_mpc_irq_update(s);
> don't you need to clear the info regs. spec says:
> the [info] register retains its value until mpc_irq is cleared.
The full sentence is "Subsequent security violating transfers
remain blocked, that is, not captured in this register
and the register retains its value until mpc_irq is cleared."
I interpret "until mpc_irq is cleared" as applying to the
entire thing, ie mpc_irq being cleared is what allows a
subsequent transfer to be captured in this register.
(Hardware actively clearing itself to zero is unlikely,
because that costs extra gates which designers don't tend
to do unless there's a reason for it.)
>From a guest point of view (which is kind of the pov the
docs are written from), the guest can't rely on the register
value once mpc_irq is cleared (because another transaction
might come along and cause the value to be overwritten).
thanks
-- PMM
- Re: [Qemu-arm] [Qemu-devel] [PATCH v2 08/13] hw/misc/tz_mpc.c: Honour the BLK_LUT settings in translate, (continued)
[Qemu-arm] [PATCH v2 02/13] iommu: Add IOMMU index argument to notifier APIs, Peter Maydell, 2018/06/04
[Qemu-arm] [PATCH v2 04/13] exec.c: Handle IOMMUs in address_space_translate_for_iotlb(), Peter Maydell, 2018/06/04
[Qemu-arm] [PATCH v2 06/13] hw/misc/tz-mpc.c: Implement registers, Peter Maydell, 2018/06/04
Re: [Qemu-arm] [PATCH v2 06/13] hw/misc/tz-mpc.c: Implement registers, Auger Eric, 2018/06/15
[Qemu-arm] [PATCH v2 05/13] hw/misc/tz-mpc.c: Implement the Arm TrustZone Memory Protection Controller, Peter Maydell, 2018/06/04
[Qemu-arm] [PATCH v2 09/13] hw/core/or-irq: Support more than 16 inputs to an OR gate, Peter Maydell, 2018/06/04