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[Qemu-arm] [PATCH v2] don't hardcode EL1 in extended_addresses_enabled
From: |
Stefano Stabellini |
Subject: |
[Qemu-arm] [PATCH v2] don't hardcode EL1 in extended_addresses_enabled |
Date: |
Wed, 25 Oct 2017 16:28:12 -0700 (PDT) |
User-agent: |
Alpine 2.10 (DEB 1266 2009-07-14) |
extended_addresses_enabled calls arm_el_is_aa64, hardcoding exception
level 1. Instead, add an additional "el" argument to
extended_addresses_enabled.
The caller will pass the right value. In most cases, it will be
arm_current_el(env). However, arm_debug_excp_handler will
use arm_debug_target_el(env), as the target el for a debug trap can be
different from the current el.
Signed-off-by: Stefano Stabellini <address@hidden>
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 96113fe..2298428 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -500,7 +500,7 @@ static void contextidr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
ARMCPU *cpu = arm_env_get_cpu(env);
if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA)
- && !extended_addresses_enabled(env)) {
+ && !extended_addresses_enabled(env, arm_current_el(env))) {
/* For VMSA (when not using the LPAE long descriptor page table
* format) this register includes the ASID, so do a TLB flush.
* For PMSA it is purely a process ID and no action is needed.
@@ -2162,7 +2162,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t
value,
ret = get_phys_addr(env, value, access_type, mmu_idx,
&phys_addr, &attrs, &prot, &page_size, &fsr, &fi);
- if (extended_addresses_enabled(env)) {
+ if (extended_addresses_enabled(env, arm_current_el(env))) {
/* fsr is a DFSR/IFSR value for the long descriptor
* translation table format, but with WnR always clear.
* Convert it to a 64-bit PAR.
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 43106a2..6792df2 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -217,10 +217,10 @@ static inline unsigned int arm_pamax(ARMCPU *cpu)
* This is always the case if our translation regime is 64 bit,
* but depends on TTBCR.EAE for 32 bit.
*/
-static inline bool extended_addresses_enabled(CPUARMState *env)
+static inline bool extended_addresses_enabled(CPUARMState *env, unsigned int
el)
{
- TCR *tcr = &env->cp15.tcr_el[arm_is_secure(env) ? 3 : 1];
- return arm_el_is_aa64(env, 1) ||
+ TCR *tcr = &env->cp15.tcr_el[el];
+ return arm_el_is_aa64(env, el) ||
(arm_feature(env, ARM_FEATURE_LPAE) && (tcr->raw_tcr & TTBCR_EAE));
}
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 3914145..4f46eb8 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -1378,7 +1378,7 @@ void arm_debug_excp_handler(CPUState *cs)
cs->watchpoint_hit = NULL;
- if (extended_addresses_enabled(env)) {
+ if (extended_addresses_enabled(env, arm_debug_target_el(env))) {
env->exception.fsr = (1 << 9) | 0x22;
} else {
env->exception.fsr = 0x2;
@@ -1402,7 +1402,7 @@ void arm_debug_excp_handler(CPUState *cs)
return;
}
- if (extended_addresses_enabled(env)) {
+ if (extended_addresses_enabled(env, arm_debug_target_el(env))) {
env->exception.fsr = (1 << 9) | 0x22;
} else {
env->exception.fsr = 0x2;
- [Qemu-arm] [PATCH v2] don't hardcode EL1 in extended_addresses_enabled,
Stefano Stabellini <=
- Re: [Qemu-arm] [PATCH v2] don't hardcode EL1 in extended_addresses_enabled, Peter Maydell, 2017/10/30
- Re: [Qemu-arm] [PATCH v2] don't hardcode EL1 in extended_addresses_enabled, Stefano Stabellini, 2017/10/30
- Re: [Qemu-arm] [PATCH v2] don't hardcode EL1 in extended_addresses_enabled, Peter Maydell, 2017/10/31
- Re: [Qemu-arm] [PATCH v2] don't hardcode EL1 in extended_addresses_enabled, Stefano Stabellini, 2017/10/31
- Re: [Qemu-arm] [PATCH v2] don't hardcode EL1 in extended_addresses_enabled, Peter Maydell, 2017/10/31
- Re: [Qemu-arm] [PATCH v2] don't hardcode EL1 in extended_addresses_enabled, Stefano Stabellini, 2017/10/31
- Re: [Qemu-arm] [PATCH v2] don't hardcode EL1 in extended_addresses_enabled, Peter Maydell, 2017/10/31