RE: include question

[Dill, John]

>%% "Dill, John" <address@hidden> writes:
>
>  dj> I have a question about the include directive.  I have two files,
>  dj> where one includes the other.  In each of these files, they both
>  dj> include a common file.  Is that common file included twice?
>
>Yes.  Just like C.
>
>  dj> I have a few makefile functions that I've implemented which build
>  dj> off of each other, and I have tended to include every file for
>  dj> which a user-defined function is used.  But I find this is
>  dj> affecting the make response time, in the realm of seconds now on a
>  dj> slower machine.  My guess is that this can be due to multiple
>  dj> inclusion of the same files.  Is this a possibility?
>
>Could be.
>
>You can use the same tricks with make that have been used with C for 30
>years:
>
>    $ cat defs.mk
>
>    ifndef _defs.mk
>    _defs.mk := 1
>
>        ...
>
>    endif
>
>If you don't even want to try reading the file at all when it's already
>been included, you have to put the ifndef around the include statement:
>
>    ifndef _defs.mk
>    include defs.mk
>    endif

That's nice to know, but it seems a little too verbose.  I'd like to do 
something more to the effect of 'include $(call guard,defs.mk)' or '$(call 
include_guard,defs.mk)' where guard would do something to check the appropriate 
tag.

Also, can you implement something like '$(call function,defs.mk)' which will 
return the text of 'include defs.mk' if that test passes, and make will perform 
the include.

Also, can functions be used reliably to define variables?  Something like:

$(call tx_include_name,defs.mk):=1

which would expand to:

_defs_mk:=1

or some other algorithm.

I'd rather have a function define the text used for the variable than leave it 
up to the user.

Thanks for the quick response!
John