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[Guile-commits] 256/437: X86: %r12 may be used as an index register.


From: Andy Wingo
Subject: [Guile-commits] 256/437: X86: %r12 may be used as an index register.
Date: Mon, 2 Jul 2018 05:14:32 -0400 (EDT)

wingo pushed a commit to branch lightning
in repository guile.

commit 1bd169cfa34d1ec3a956e6656dbe1179dac6815f
Author: pcpa <address@hidden>
Date:   Mon Sep 30 13:30:21 2013 -0300

    X86: %r12 may be used as an index register.
    
        * lib/jit_x86-cpu.c: Correct not properly tested case of using
        %r12 as index register, what was causing an invalid assertion.
        %r12 is mapped to the "extra" JIT_R3 register, and test cases
        only test "standard" lightning registers.
---
 ChangeLog         | 7 +++++++
 lib/jit_x86-cpu.c | 3 ++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/ChangeLog b/ChangeLog
index 80e14b3..60851b3 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,10 @@
+2013-10-30 Paulo Andrade <address@hidden>
+
+       * lib/jit_x86-cpu.c: Correct not properly tested case of using
+       %r12 as index register, what was causing an invalid assertion.
+       %r12 is mapped to the "extra" JIT_R3 register, and test cases
+       only test "standard" lightning registers.
+
 2013-10-28 Paulo Andrade <address@hidden>
 
        * lib/jit_ia64.c: Minor change to force collecting the maximum
diff --git a/lib/jit_x86-cpu.c b/lib/jit_x86-cpu.c
index afc83d2..4cf16c1 100644
--- a/lib/jit_x86-cpu.c
+++ b/lib/jit_x86-cpu.c
@@ -61,6 +61,7 @@
 #  define _R14_REGNO                   14
 #  define _R15_REGNO                   15
 #  define r7(reg)                      (reg & 7)
+#  define r8(reg)                      (reg & 15)
 #  define _SCL1                                0x00
 #  define _SCL2                                0x01
 #  define _SCL4                                0x02
@@ -701,7 +702,7 @@ _rx(jit_state_t *_jit, jit_int32_t rd, jit_int32_t md,
        sib(ms, r7(ri), 0x05);
        ii(md);
     }
-    else if (r7(ri) != _RSP_REGNO) {
+    else if (r8(ri) != _RSP_REGNO) {
        if (md == 0 && r7(rb) != _RBP_REGNO) {
            mrm(0x00, r7(rd), 0x04);
            sib(ms, r7(ri), r7(rb));



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