[Guile-commits] 219/437: Remove redundancy in the hppa cache synchronization code.

[Andy Wingo]

wingo pushed a commit to branch lightning
in repository guile.

commit 443b7467c82c9c3edda5014e558997717396db45
Author: pcpa <address@hidden>
Date:   Mon Jun 10 16:23:44 2013 -0300

    Remove redundancy in the hppa cache synchronization code.
    
        * lib/jit_hppa.c: Sanitize the cache synchronization inline
        assembly code that was doing twice the work and redundantly
        flushing the end address every loop iteration.
---
 ChangeLog      |  6 ++++++
 lib/jit_hppa.c | 11 +++++------
 2 files changed, 11 insertions(+), 6 deletions(-)

diff --git a/ChangeLog b/ChangeLog
index fefd19d..97357a4 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,9 @@
+2013-06-10 Paulo Andrade <address@hidden>
+
+       * lib/jit_hppa.c: Sanitize the cache synchronization inline
+       assembly code that was doing twice the work and redundantly
+       flushing the end address every loop iteration.
+
 2013-06-09 Paulo Andrade <address@hidden>
 
        * configure.ac, check/Makefile.am, doc/Makefile.am: Do not
diff --git a/lib/jit_hppa.c b/lib/jit_hppa.c
index 43b43c2..f403c73 100644
--- a/lib/jit_hppa.c
+++ b/lib/jit_hppa.c
@@ -1176,6 +1176,7 @@ of being modified.
   Adapted from ffcall/trampoline/cache-hppa.c:__TR_clear_cache to
 loop over addresses as it is unlikely from and to addresses would fit in
 at most two cachelines.
+  FIXME A cache line can be 16, 32, or 64 bytes.
  */
     /*
      * Copyright 1995-1997 Bruno Haible, <address@hidden>
@@ -1186,18 +1187,16 @@ at most two cachelines.
      * on this software.
      */
     {
-       /* FIXME this may be required on Linux or other OSes with
-        * multiprocessor support (was not required for the hppa
-        * port done on Debian hppa...) */
        jit_word_t      f = (jit_word_t)_jit->code.ptr;
+       jit_word_t      n = f + 32;
        jit_word_t      t = f + _jit->code.length;
        register int    u, v;
-       for (; f <= t; f += 32) {
+       for (; f <= t; n = f + 32, f += 64) {
            asm volatile ("fdc 0(0,%0)"
                          "\n\t" "fdc 0(0,%1)"
                          "\n\t" "sync"
                          :
-                         : "r" (f), "r" (t)
+                         : "r" (f), "r" (n)
                          );
            asm volatile ("mfsp %%sr0,%1"
                          "\n\t" "ldsid (0,%4),%0"
@@ -1213,7 +1212,7 @@ at most two cachelines.
                          "\n\t" "nop"
                          "\n\t" "nop"
                          : "=r" (u), "=r" (v)
-                         : "r" (f), "r" (t), "r" (f)
+                         : "r" (f), "r" (n), "r" (f)
                          );
        }
     }