[Gnewsense-dev] Re: [lemote] gNewSense Lemote Yeeloong 2.6.30 linux - please test this build

[yanhua]

zhangfx 写道:
> We need a patch for compiler to work around a known bug that can lead
> to hard lock.
>
> Dear Yanhua, you can arrange to send the patch to gNewsense developers.
>
> Regards
>
> Danny Clark 写道:
>> Danny Clark wrote:
>> Drat, just had a hard lockup during the compile. I don't have more time
>> to look at this now, but if you do, here is an email that describes how
>> we may be able to get some debug information for the hangs:


-- 
晏华


diff --git a/gas/config/tc-mips.c b/gas/config/tc-mips.c
index f55961b..8c1e132 100644
--- a/gas/config/tc-mips.c
+++ b/gas/config/tc-mips.c
@@ -759,6 +759,9 @@ static int mips_fix_vr4120;
 /* ...likewise -mfix-vr4130.  */
 static int mips_fix_vr4130;
 
+/* True if -mfix-ls2f-kernel.  */
+static int mips_fix_ls2f_kernel;
+
 /* We don't relax branches by default, since this causes us to expand
    `la .l2 - .l1' if there's a branch between .l1 and .l2, because we
    fail to compute the offset before expanding the macro to the most
@@ -3874,6 +3877,27 @@ normalize_address_expr (expressionS *ex)
 }
 
 /*
+ * Eliminate instruction fetch from outside 256M region.
+ * jr target pc &= 'hffff_ffff_cfff_ffff
+ * FOR KERNEL ONLY
+ */
+static void
+macro_build_jrpatch (expressionS *ex, unsigned int sreg)
+{
+  if (mips_fix_ls2f_kernel && sreg != 26 && sreg != 27 && sreg != ATREG) {
+    int oldat=mips_opts.at;
+    mips_opts.at=ATREG;
+    ex->X_op = O_constant;
+    ex->X_add_number = 0xcfff0000;
+    macro_build (ex, "lui", "t,u", AT, BFD_RELOC_HI16);
+    ex->X_add_number = 0xffff;
+    macro_build (ex, "ori", "t,r,i", AT, AT, BFD_RELOC_LO16);
+    macro_build (NULL, "and", "d,v,t", sreg, sreg, AT);
+    mips_opts.at=oldat;
+  } 
+}
+
+/*
  * Generate a "jalr" instruction with a relocation hint to the called
  * function.  This occurs in NewABI PIC code.
  */
@@ -3887,6 +3911,7 @@ macro_build_jalr (expressionS *ep)
       frag_grow (8);
       f = frag_more (0);
     }
+  macro_build_jrpatch (ep, PIC_CALL_REG);
   macro_build (NULL, "jalr", "d,s", RA, PIC_CALL_REG);
   if (HAVE_NEWABI)
     fix_new_exp (frag_now, f - frag_now->fr_literal,
@@ -6032,6 +6057,26 @@ macro (struct mips_cl_insn *ip)
        macro_build (NULL, ADDRESS_ADD_INSN, "d,v,t", treg, tempreg, breg);
       break;
 
+    case M_JR_S:
+       macro_build_jrpatch (&expr1, sreg);     
+        macro_build (NULL, "jr", "s", sreg);
+       break;
+
+    case M_J_S:
+       macro_build_jrpatch (&expr1, sreg);     
+       macro_build (NULL, "j", "s", sreg);
+       break; 
+
+    case M_JALR_S:
+       macro_build_jrpatch (&expr1, sreg);     
+       macro_build (NULL, "jalr", "s", sreg);
+       break;
+
+    case M_JALR_DS:
+       macro_build_jrpatch (&expr1, sreg);     
+        macro_build (NULL, "jalr", "d,s", dreg, sreg);
+       break;
+
     case M_J_A:
       /* The j instruction may not be used in PIC code, since it
         requires an absolute address.  We convert it to a b
@@ -6050,12 +6095,16 @@ macro (struct mips_cl_insn *ip)
       /* Fall through.  */
     case M_JAL_2:
       if (mips_pic == NO_PIC)
-       macro_build (NULL, "jalr", "d,s", dreg, sreg);
+      {
+         macro_build_jrpatch (&expr1, sreg);   
+         macro_build (NULL, "jalr", "d,s", dreg, sreg);
+      }
       else
        {
          if (sreg != PIC_CALL_REG)
            as_warn (_("MIPS PIC call to register other than $25"));
 
+         macro_build_jrpatch (&expr1, sreg);   
          macro_build (NULL, "jalr", "d,s", dreg, sreg);
          if (mips_pic == SVR4_PIC && !HAVE_NEWABI)
            {
@@ -11179,9 +11228,11 @@ struct option md_longopts[] =
 #define OPTION_NO_FIX_VR4130 (OPTION_FIX_BASE + 5)
   {"mfix-vr4130",    no_argument, NULL, OPTION_FIX_VR4130},
   {"mno-fix-vr4130", no_argument, NULL, OPTION_NO_FIX_VR4130},
+#define OPTION_FIX_LS2F_KERNEL (OPTION_FIX_BASE + 6)
+  {"mfix-ls2f-kernel", no_argument, NULL, OPTION_FIX_LS2F_KERNEL},
 
   /* Miscellaneous options.  */
-#define OPTION_MISC_BASE (OPTION_FIX_BASE + 6)
+#define OPTION_MISC_BASE (OPTION_FIX_BASE + 7)
 #define OPTION_TRAP (OPTION_MISC_BASE + 0)
   {"trap", no_argument, NULL, OPTION_TRAP},
   {"no-break", no_argument, NULL, OPTION_TRAP},
@@ -11479,6 +11530,10 @@ md_parse_option (int c, char *arg)
       mips_fix_vr4130 = 0;
       break;
 
+    case OPTION_FIX_LS2F_KERNEL:
+      mips_fix_ls2f_kernel = 1;
+      break;
+
     case OPTION_RELAX_BRANCH:
       mips_relax_branch = 1;
       break;
@@ -11694,6 +11749,8 @@ mips_set_architecture (const struct mips_cpu_info *info)
       mips_opts.arch = info->cpu;
       mips_opts.isa = info->isa;
     }
+  if (mips_fix_ls2f_kernel)
+      mips_opts.arch = CPU_LOONGSON_2F;
 }
 
 
diff --git a/include/opcode/mips.h b/include/opcode/mips.h
index 8d201f6..d0a61c8 100644
--- a/include/opcode/mips.h
+++ b/include/opcode/mips.h
@@ -758,7 +758,11 @@ enum
   M_DSUB_I,
   M_DSUBU_I,
   M_DSUBU_I_2,
+  M_JR_S,
+  M_J_S, /*JCX*/
   M_J_A,
+  M_JALR_S,
+  M_JALR_DS,
   M_JAL_1,
   M_JAL_2,
   M_JAL_A,
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 82a01f8..933b932 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -186,7 +186,7 @@ const struct mips_opcode mips_builtin_opcodes[] =
 /* name,    args,      match,      mask,       pinfo,                  pinfo2, 
        membership */
 {"pref",    "k,o(b)",   0xcc000000, 0xfc000000, RD_b,                  0,      
        I4_32|G3        },
 {"prefx",   "h,t(b)",  0x4c00000f, 0xfc0007ff, RD_b|RD_t|FP_S,         0,      
        I4_33   },
-{"nop",     "",         0x00000000, 0xffffffff, 0,                     
INSN2_ALIAS,    I1      }, /* sll */
+{"nop",     "",         0x00020021, 0xffffffff, 0,                     
INSN2_ALIAS,    I1      }, /* addu */
 {"ssnop",   "",         0x00000040, 0xffffffff, 0,                     
INSN2_ALIAS,    I32|N55 }, /* sll */
 {"ehb",     "",         0x000000c0, 0xffffffff, 0,                     
INSN2_ALIAS,    I33     }, /* sll */
 {"li",      "t,j",      0x24000000, 0xffe00000, WR_t,                  
INSN2_ALIAS,    I1      }, /* addiu */
@@ -710,10 +710,12 @@ const struct mips_opcode mips_builtin_opcodes[] =
 {"floor.w.s", "D,S",   0x4600000f, 0xffff003f, WR_D|RD_S|FP_S,         0,      
        I2      },
 {"hibernate","",        0x42000023, 0xffffffff,        0,                      
0,              V1      },
 {"ins",     "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s,                    
0,              I33     },
+{"jr",      "s",       0x0,    (int) M_JR_S,   INSN_MACRO,             0,      
        IL2F    },
 {"jr",      "s",       0x00000008, 0xfc1fffff, UBD|RD_s,               0,      
        I1      },
 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
    the same hazard barrier effect.  */
 {"jr.hb",   "s",       0x00000408, 0xfc1fffff, UBD|RD_s,               0,      
        I32     },
+{"j",       "s",       0,     (int) M_J_S,     INSN_MACRO,             0,      
        IL2F    }, /* jcx */
 {"j",       "s",       0x00000008, 0xfc1fffff, UBD|RD_s,               0,      
        I1      }, /* jr */
 /* SVR4 PIC code requires special handling for j, so it must be a
    macro.  */
@@ -722,7 +724,9 @@ const struct mips_opcode mips_builtin_opcodes[] =
    assembler, but will never match user input (because the line above
    will match first).  */
 {"j",       "a",       0x08000000, 0xfc000000, UBD,                    0,      
        I1      },
+{"jalr",    "s",       0,     (int) M_JALR_S,  INSN_MACRO,             0,      
        IL2F    },
 {"jalr",    "s",       0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d,          0,      
        I1      },
+{"jalr",    "d,s",     0,     (int) M_JALR_DS, INSN_MACRO,             0,      
        IL2F    },
 {"jalr",    "d,s",     0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d,          0,      
        I1      },
 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
    with the same hazard barrier effect.  */