[Commit-gnuradio] r8131 - usrp2/trunk/fpga/top/u2_rev2

[matt]

Author: matt
Date: 2008-03-28 15:23:51 -0600 (Fri, 28 Mar 2008)
New Revision: 8131

Modified:
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ise
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj
   usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf
Log:
rev 10.1 compatible


Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ise
===================================================================
(Binary files differ)

Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj    2008-03-28 21:22:48 UTC (rev 
8130)
+++ usrp2/trunk/fpga/top/u2_rev2/u2_rev2.prj    2008-03-28 21:23:51 UTC (rev 
8131)
@@ -24,25 +24,24 @@
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v"
 verilog work "../../opencores/8b10b/encode_8b10b.v"
 verilog work "../../opencores/8b10b/decode_8b10b.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v"
 verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
 verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
 verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
-verilog work "../../eth/rtl/verilog/Reg_int.v"
-verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v"
-verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v"
 verilog work "../../eth/rtl/verilog/MAC_tx/Random_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v"
 verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v"
 verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
-verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v"
 verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
 verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
 verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
-verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
 verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
 verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
 verilog work "../../control_lib/fifo_2clock_casc.v"
+verilog work "../../control_lib/CRC16_D16.v"
 verilog work "../../control_lib/cascadefifo2.v"
-verilog work "../../control_lib/CRC16_D16.v"
 verilog work "../../timing/time_sender.v"
 verilog work "../../timing/time_receiver.v"
 verilog work "../../serdes/serdes_tx.v"
@@ -60,13 +59,14 @@
 verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v"
 verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_edk32.v"
-verilog work "../../eth/rtl/verilog/flow_ctrl_tx.v"
-verilog work "../../eth/rtl/verilog/flow_ctrl_rx.v"
-verilog work "../../eth/rtl/verilog/eth_miim.v"
 verilog work "../../eth/rtl/verilog/RMON.v"
+verilog work "../../eth/rtl/verilog/Reg_int.v"
 verilog work "../../eth/rtl/verilog/Phy_int.v"
 verilog work "../../eth/rtl/verilog/MAC_tx.v"
 verilog work "../../eth/rtl/verilog/MAC_rx.v"
+verilog work "../../eth/rtl/verilog/flow_ctrl_tx.v"
+verilog work "../../eth/rtl/verilog/flow_ctrl_rx.v"
+verilog work "../../eth/rtl/verilog/eth_miim.v"
 verilog work "../../eth/rtl/verilog/Clk_ctrl.v"
 verilog work "../../control_lib/strobe_gen.v"
 verilog work "../../control_lib/setting_reg.v"
@@ -77,8 +77,8 @@
 verilog work "../../control_lib/decoder_3_8.v"
 verilog work "../../control_lib/dcache.v"
 verilog work "../../control_lib/buffer_int.v"
+verilog work "../../timing/time_sync.v"
 verilog work "../../timing/timer.v"
-verilog work "../../timing/time_sync.v"
 verilog work "../../serdes/serdes.v"
 verilog work "../../sdr_lib/tx_control.v"
 verilog work "../../sdr_lib/rx_control.v"
@@ -102,5 +102,5 @@
 verilog work "../../control_lib/extram_interface.v"
 verilog work "../../control_lib/buffer_pool.v"
 verilog work "../../control_lib/atr_controller.v"
-verilog work "../u2_basic/u2_basic.v"
+verilog work "../u2_core/u2_core.v"
 verilog work "u2_rev2.v"

Modified: usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf
===================================================================
--- usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf    2008-03-28 21:22:48 UTC (rev 
8130)
+++ usrp2/trunk/fpga/top/u2_rev2/u2_rev2.ucf    2008-03-28 21:23:51 UTC (rev 
8131)
@@ -320,3 +320,8 @@
 
 NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
 TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+
+
+NET "GMII_RX_CLK" CLOCK_DEDICATED_ROUTE = FALSE; 
+NET "cpld_clk" CLOCK_DEDICATED_ROUTE = FALSE;
+NET "PHY_CLK" CLOCK_DEDICATED_ROUTE = FALSE;