[Commit-gnuradio] r8130 - usrp2/trunk/fpga/top/u2_core

[matt]

Author: matt
Date: 2008-03-28 15:22:48 -0600 (Fri, 28 Mar 2008)
New Revision: 8130

Modified:
   usrp2/trunk/fpga/top/u2_core/u2_core.v
Log:
first simple changes to get pins right


Modified: usrp2/trunk/fpga/top/u2_core/u2_core.v
===================================================================
--- usrp2/trunk/fpga/top/u2_core/u2_core.v      2008-03-28 20:45:49 UTC (rev 
8129)
+++ usrp2/trunk/fpga/top/u2_core/u2_core.v      2008-03-28 21:22:48 UTC (rev 
8130)
@@ -1,8 +1,8 @@
 // 
////////////////////////////////////////////////////////////////////////////////
-// Module Name:    u2_basic
+// Module Name:    u2_core
 // 
////////////////////////////////////////////////////////////////////////////////
 
-module u2_basic
+module u2_core
   (// Clocks
    input dsp_clk,
    input wb_clk,
@@ -11,8 +11,7 @@
    input pps_in,
    
    // Misc, debug
-   output led1,
-   output led2,
+   output [7:0] leds,
    output [31:0] debug,
    output [1:0] debug_clk,
 
@@ -379,11 +378,10 @@
    assign       s7_dat_i = 32'd0;
 
    // Output control lines
-   wire [7:0]   clock_outs, serdes_outs, adc_outs, misc_outs;
+   wire [7:0]   clock_outs, serdes_outs, adc_outs;
    assign       {clock_ready, clk_en[1:0], clk_sel[1:0]} = clock_outs[4:0];
    assign       {ser_enable, ser_prbsen, ser_loopen, ser_rx_en} = 
serdes_outs[3:0];
    assign       {adc_oe_a, adc_on_a, adc_oe_b, adc_on_b } = adc_outs[3:0];
-   assign       {led2, led1} = misc_outs[1:0];
 
    wire         phy_reset;
    assign       PHY_RESETn = ~phy_reset;
@@ -395,7 +393,7 @@
    setting_reg #(.my_addr(2)) sr_adc 
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
                                      .in(set_data),.out(adc_outs),.changed());
    setting_reg #(.my_addr(3)) sr_led 
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
-                                     .in(set_data),.out(misc_outs),.changed());
+                                     .in(set_data),.out(leds),.changed());
    setting_reg #(.my_addr(4)) sr_phy 
(.clk(wb_clk),.rst(wb_rst),.strobe(set_stb),.addr(set_addr),
                                      .in(set_data),.out(phy_reset),.changed());
 
@@ -621,8 +619,8 @@
                                 { ser_r[15:8] },
                                 { ser_r[7:0] } };
 */
-   wire [31:0] debug_serdes_receiver = {uart_tx_o,debug_serdes2[30:0]};
-   wire [31:0] debug_serdes_sender = { uart_tx_o, debug_serdes0[30:0]};
+   wire [31:0] debug_serdes_receiver = debug_serdes2;
+   wire [31:0] debug_serdes_sender = debug_serdes0;
    wire [31:0] debug_serdes_common = debug_serdes1;
    
    /*
@@ -643,4 +641,4 @@
    //assign      debug_gpio_0 = debug_serdes_sender;
    assign      debug_gpio_1 = {uart_tx_o, debug_serdes1[30:0]};
    
-endmodule // u2_basic
+endmodule // u2_core