[Commit-gnuradio] r8024 - usrp2/trunk/fpga/serdes

[matt]

Author: matt
Date: 2008-03-14 12:28:53 -0600 (Fri, 14 Mar 2008)
New Revision: 8024

Modified:
   usrp2/trunk/fpga/serdes/serdes.v
Log:
more debugging


Modified: usrp2/trunk/fpga/serdes/serdes.v
===================================================================
--- usrp2/trunk/fpga/serdes/serdes.v    2008-03-14 18:28:34 UTC (rev 8023)
+++ usrp2/trunk/fpga/serdes/serdes.v    2008-03-14 18:28:53 UTC (rev 8024)
@@ -14,7 +14,8 @@
      output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output 
wr_error_o,
      input wr_ready_i, input wr_full_i,
      
-     output [31:0] debug);
+     output [31:0] debug0, 
+     output [31:0] debug1);
 
    wire [15:0] fifo_space;
    wire        xon_rcvd, xoff_rcvd, inhibit_tx, send_xon, send_xoff, sent;
@@ -25,7 +26,8 @@
       
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
       
.rd_dat_i(rd_dat_i),.rd_read_o(rd_read_o),.rd_done_o(rd_done_o),.rd_error_o(rd_error_o),
       .rd_sop_i(rd_sop_i),.rd_eop_i(rd_eop_i),
-      .inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff), 
.sent(sent) );
+      .inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff), 
.sent(sent),
+      .debug(debug_tx) );
    
    serdes_rx #(.FIFOSIZE(RXFIFOSIZE)) serdes_rx
      (.clk(clk),.rst(rst),
@@ -45,6 +47,15 @@
       
.fifo_space(fifo_space),.send_xon(send_xon),.send_xoff(send_xoff),.sent(sent) );
 
    //assign      debug = { fifo_space, send_xon, send_xoff, debug_rx[13:0] };
-   assign      debug = debug_rx;
+   //assign      debug = debug_rx;
+
+   assign      debug0 = { { debug_tx[3:0] /* xfer_active,state[2:0] */, 
rd_read_o, rd_done_o, rd_sop_i, rd_eop_i },
+                         { debug_tx[5:4] /* full,empty */ , inhibit_tx, 
send_xon, send_xoff, sent, ser_tkmsb, ser_tklsb},
+                         { ser_t[15:8] },
+                         { ser_t[7:0] } };
    
+   assign      debug1 = { { debug_rx[7:0] }, /*  
odd,xfer_active,sop_i,eop_i,error_i,state[2:0] */
+                         { wr_write_o, wr_error_o, wr_ready_i, wr_done_i, /* 
xon_rcvd */ debug_rx[7] /* odd */, xoff_rcvd, ser_rkmsb, ser_rklsb },
+                         { ser_r[15:8] },
+                         { ser_r[7:0] } };
 endmodule // serdes