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[Commit-gnuradio] r8008 - usrp2/trunk/fpga/control_lib
From: |
matt |
Subject: |
[Commit-gnuradio] r8008 - usrp2/trunk/fpga/control_lib |
Date: |
Wed, 12 Mar 2008 14:29:19 -0600 (MDT) |
Author: matt
Date: 2008-03-12 14:29:18 -0600 (Wed, 12 Mar 2008)
New Revision: 8008
Modified:
usrp2/trunk/fpga/control_lib/fifo_2clock_casc.v
Log:
syntax cleanup
Modified: usrp2/trunk/fpga/control_lib/fifo_2clock_casc.v
===================================================================
--- usrp2/trunk/fpga/control_lib/fifo_2clock_casc.v 2008-03-12 20:26:37 UTC
(rev 8007)
+++ usrp2/trunk/fpga/control_lib/fifo_2clock_casc.v 2008-03-12 20:29:18 UTC
(rev 8008)
@@ -1,10 +1,13 @@
module fifo_2clock_casc
#(parameter DWIDTH=32, AWIDTH=9)
- (input wclk, input [DWIDTH-1:0] datain, input write, output full, output
reg [AWIDTH-1:0] level_wclk,
- input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output
reg [AWIDTH-1:0] level_rclk,
+ (input wclk, input [DWIDTH-1:0] datain, input write, output full, output
[AWIDTH-1:0] level_wclk,
+ input rclk, output [DWIDTH-1:0] dataout, input read, output empty, output
[AWIDTH-1:0] level_rclk,
input arst);
+ wire full_int, empty_int, full_int2, empty_int2, transfer, transfer2;
+ wire [DWIDTH-1:0] data_int, data_int2;
+
shortfifo #(.WIDTH(DWIDTH)) shortfifo
(.clk(wclk), .rst(arst), .clear(0),
.datain(datain), .write(write), .full(full),
@@ -12,14 +15,14 @@
assign transfer = ~full_int & ~empty_int;
- fifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH))
+ fifo_2clock #(.DWIDTH(DWIDTH),.AWIDTH(AWIDTH)) fifo_2clock
(.wclk(wclk), .datain(data_int), .write(transfer), .full(full_int),
.level_wclk(level_wclk),
.rclk(rclk), .dataout(data_int2), .read(transfer2), .empty(empty_int2),
.level_rclk(level_rclk),
.arst(arst) );
assign transfer2 = ~full_int2 & ~empty_int2;
- shortfifo #(.WIDTH(DWIDTH))
+ shortfifo #(.WIDTH(DWIDTH)) shortfifo2
(.clk(rclk), .rst(arst), .clear(0),
.datain(data_int2), .write(transfer2), .full(full_int2),
.dataout(dataout), .read(read), .empty(empty) );
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