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[Commit-gnuradio] r7987 - in gnuradio/branches/developers/gnychis/fpga/u
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From: |
gnychis |
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Subject: |
[Commit-gnuradio] r7987 - in gnuradio/branches/developers/gnychis/fpga/usrp/fpga: inband_lib toplevel/usrp_inband_usb |
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Date: |
Tue, 11 Mar 2008 12:29:04 -0600 (MDT) |
Author: gnychis
Date: 2008-03-11 12:29:04 -0600 (Tue, 11 Mar 2008)
New Revision: 7987
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/cmd_reader.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/config.vh
Log:
the use of adc_time to represent the timestamp is a little bit difficult to
recognize when reading the code, using timestamp_clock is much more forward
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/chan_fifo_reader.v
2008-03-11 06:57:11 UTC (rev 7986)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/chan_fifo_reader.v
2008-03-11 18:29:04 UTC (rev 7987)
@@ -1,12 +1,12 @@
module chan_fifo_reader
- (reset, tx_clock, tx_strobe, adc_time, samples_format,
+ (reset, tx_clock, tx_strobe, timestamp_clock, samples_format,
fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
input wire reset ;
input wire tx_clock ;
input wire tx_strobe ; //signal to output tx_i and
tx_q
- input wire [31:0] adc_time ; //current time
+ input wire [31:0] timestamp_clock ; //current time
input wire [3:0] samples_format ;// not useful at this point
input wire [31:0] fifodata ; //the data input
input wire pkt_waiting ; //signal the next packet is
ready
@@ -146,7 +146,7 @@
time_wait <= time_wait + 32'd1;
// Outdated
- if ((timestamp < adc_time) ||
+ if ((timestamp < timestamp_clock) ||
(time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
begin
trash <= 1;
@@ -154,8 +154,8 @@
skip <= 1;
end
// Let's send it
- else if ((timestamp <= adc_time + `JITTER
- && timestamp > adc_time)
+ else if ((timestamp <= timestamp_clock + `JITTER
+ && timestamp > timestamp_clock)
|| timestamp == 32'hFFFFFFFF)
begin
if (rssi <= threshhold || rssi_flag == 0)
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/cmd_reader.v
===================================================================
--- gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/cmd_reader.v
2008-03-11 06:57:11 UTC (rev 7986)
+++ gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/cmd_reader.v
2008-03-11 18:29:04 UTC (rev 7987)
@@ -1,6 +1,6 @@
module cmd_reader
(//System
- input reset, input txclk, input [31:0] adc_time,
+ input reset, input txclk, input [31:0] timestamp_clock,
//FX2 Side
output reg skip, output reg rdreq,
input [31:0] fifodata, input pkt_waiting,
@@ -96,15 +96,15 @@
WAIT :
begin
// Let's send it
- if ((value0 <= adc_time + `JITTER
- && value0 > adc_time)
+ if ((value0 <= timestamp_clock + `JITTER
+ && value0 > timestamp_clock)
|| value0 == 32'hFFFFFFFF)
state <= TEST;
// Wait a little bit more
- else if (value0 > adc_time + `JITTER)
+ else if (value0 > timestamp_clock + `JITTER)
state <= WAIT;
// Outdated
- else if (value0 < adc_time)
+ else if (value0 < timestamp_clock)
begin
state <= IDLE;
skip <= 1;
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/packet_builder.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/packet_builder.v
2008-03-11 06:57:11 UTC (rev 7986)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/packet_builder.v
2008-03-11 18:29:04 UTC (rev 7987)
@@ -2,7 +2,7 @@
// System
input rxclk,
input reset,
- input [31:0] adctime,
+ input [31:0] timestamp_clock,
input [3:0] channels,
// ADC side
input [15:0]chan_fifodata,
@@ -43,7 +43,7 @@
reg [2:0] state;
reg [8:0] read_length;
reg [8:0] payload_len;
- reg tstamp_complete;
+ reg timestamp_complete;
reg [3:0] check_next;
wire [31:0] true_rssi;
@@ -68,7 +68,7 @@
WR <= 0;
rd_select <= 0;
chan_rdreq <= 0;
- tstamp_complete <= 0;
+ timestamp_complete <= 0;
check_next <= 0;
state <= `IDLE;
end
@@ -119,13 +119,13 @@
end
`TIMESTAMP: begin
- fifodata <= #1 (tstamp_complete ? adctime[31:16] :
adctime[15:0]);
- tstamp_complete <= #1 ~tstamp_complete;
+ fifodata <= #1 (timestamp_complete ? timestamp_clock[31:16] :
timestamp_clock[15:0]);
+ timestamp_complete <= #1 ~timestamp_complete;
- if (~tstamp_complete)
+ if (~timestamp_complete)
chan_rdreq <= #1 1;
- state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP);
+ state <= #1 (timestamp_complete ? `FORWARD : `TIMESTAMP);
end
`FORWARD: begin
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
2008-03-11 06:57:11 UTC (rev 7986)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/rx_buffer_inband.v
2008-03-11 18:29:04 UTC (rev 7987)
@@ -51,12 +51,12 @@
read_count <= #1 RD ? read_count : 9'b0;
// Time counter
- reg [31:0] adctime;
+ reg [31:0] timestamp_clock;
always @(posedge rxclk)
if (reset)
- adctime <= 0;
+ timestamp_clock <= 0;
else
- adctime <= adctime + 1;
+ timestamp_clock <= timestamp_clock + 1;
// USB side fifo
wire [11:0] rdusedw;
@@ -121,7 +121,7 @@
packet_builder #(NUM_CHAN) rx_pkt_builer (
.rxclk ( rxclk ),
.reset ( reset ),
- .adctime ( adctime ),
+ .timestamp_clock ( timestamp_clock ),
.channels ( NUM_CHAN ),
.chan_rdreq ( chan_rdreq ),
.chan_fifodata ( chan_fifodata ),
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
2008-03-11 06:57:11 UTC (rev 7986)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/tx_buffer_inband.v
2008-03-11 18:29:04 UTC (rev 7987)
@@ -36,7 +36,7 @@
genvar i ;
/* These will eventually be external register */
- reg [31:0] adc_time ;
+ reg [31:0] timestamp_clock ;
wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
wire [31:0] rssi [3:0];
assign rssi[0] = rssi_0;
@@ -46,9 +46,9 @@
always @(posedge txclk)
if (reset)
- adc_time <= 0;
+ timestamp_clock <= 0;
else
- adc_time <= adc_time + 1;
+ timestamp_clock <= timestamp_clock + 1;
/* Connections between tx_usb_fifo_reader and
@@ -126,7 +126,7 @@
chan_fifo_reader tx_chan_reader
(.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
- .adc_time(adc_time), .samples_format(4'b0),
+ .timestamp_clock(timestamp_clock), .samples_format(4'b0),
.tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
.skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
.fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
@@ -143,7 +143,7 @@
.RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
cmd_reader tx_cmd_reader
- (.reset(reset), .txclk(txclk), .adc_time(adc_time),
.skip(chan_skip[NUM_CHAN]),
+ (.reset(reset), .txclk(txclk), .timestamp_clock(timestamp_clock),
.skip(chan_skip[NUM_CHAN]),
.rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
.pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
.rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
Modified:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/config.vh
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/config.vh
2008-03-11 06:57:11 UTC (rev 7986)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/toplevel/usrp_inband_usb/config.vh
2008-03-11 18:29:04 UTC (rev 7987)
@@ -31,10 +31,10 @@
// ====================================================================
// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel
-// `include "../include/common_config_1rxhb_1tx.vh"
+ `include "../include/common_config_1rxhb_1tx.vh"
// Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels
- `include "../include/common_config_2rxhb_2tx.vh"
+// `include "../include/common_config_2rxhb_2tx.vh"
// Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels
//`include "../include/common_config_4rx_0tx.vh"
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