[Commit-gnuradio] r7270 - usrp2/trunk/fpga/testbench

[matt]

Author: matt
Date: 2007-12-26 12:56:43 -0700 (Wed, 26 Dec 2007)
New Revision: 7270

Modified:
   usrp2/trunk/fpga/testbench/
   usrp2/trunk/fpga/testbench/Makefile
   usrp2/trunk/fpga/testbench/cmdfile
Log:
make everything compile in its new location



Property changes on: usrp2/trunk/fpga/testbench
___________________________________________________________________
Name: svn:ignore
   + single_u2_sim
dual_u2_sim
*.lxt
*.vcd


Modified: usrp2/trunk/fpga/testbench/Makefile
===================================================================
--- usrp2/trunk/fpga/testbench/Makefile 2007-12-26 19:55:44 UTC (rev 7269)
+++ usrp2/trunk/fpga/testbench/Makefile 2007-12-26 19:56:43 UTC (rev 7270)
@@ -1,7 +1,10 @@
-all: u2_sim
+all: single dual
 
-u2_sim:        
+single:        
        iverilog -Wimplicit -Wportbind -c cmdfile 
../top/single_u2_sim/single_u2_sim.v -o single_u2_sim
 
+dual:  
+       iverilog -Wimplicit -Wportbind -c cmdfile 
../top/dual_u2_sim/dual_u2_sim.v -o dual_u2_sim
+
 clean:
-       rm -f single_u2_sim *.vcd *.lxt
+       rm -f single_u2_sim dual_u2_sim *.vcd *.lxt

Modified: usrp2/trunk/fpga/testbench/cmdfile
===================================================================
--- usrp2/trunk/fpga/testbench/cmdfile  2007-12-26 19:55:44 UTC (rev 7269)
+++ usrp2/trunk/fpga/testbench/cmdfile  2007-12-26 19:56:43 UTC (rev 7270)
@@ -1,38 +1,41 @@
+
 # My stuff
 -y .
 -y ../top/u2_basic
--y ../../control_lib
--y ../../serdes
--y ../../sdr_lib
+-y ../control_lib
+-y ../serdes
+-y ../sdr_lib
+-y ../timing
 
 # Models
--y ../../models
--y ../../models/CY7C1356C
+-y ../models
+-y ../models/CY7C1356C
 
 # Open Cores
--y ../../opencores/spi/rtl/verilog
-+incdir+../../opencores/spi/rtl/verilog
--y ../../opencores/wb_conbus/rtl/verilog
-+incdir+../../opencores/wb_conbus/rtl/verilog
--y ../../opencores/i2c/rtl/verilog
-+incdir+../../opencores/i2c/rtl/verilog
--y ../../opencores/aemb/rtl/verilog
--y ../../opencores/simple_gpio/rtl
--y ../../opencores/simple_pic/rtl
--y ../../opencores/uart16550/rtl/verilog
-+incdir+../../opencores/uart16550/rtl/verilog
+-y ../opencores/8b10b
+-y ../opencores/spi/rtl/verilog
++incdir+../opencores/spi/rtl/verilog
+-y ../opencores/wb_conbus/rtl/verilog
++incdir+../opencores/wb_conbus/rtl/verilog
+-y ../opencores/i2c/rtl/verilog
++incdir+../opencores/i2c/rtl/verilog
+-y ../opencores/aemb/rtl/verilog
+-y ../opencores/simple_gpio/rtl
+-y ../opencores/simple_pic/rtl
+-y ../opencores/uart16550/rtl/verilog
++incdir+../opencores/uart16550/rtl/verilog
 
 # Ethernet
-+incdir+../../eth/rtl/verilog
--y ../../eth/rtl/verilog
--y ../../eth/rtl/verilog/MAC_tx
--y ../../eth/rtl/verilog/MAC_rx
--y ../../eth/rtl/verilog/miim
--y ../../eth/rtl/verilog/TECH
--y ../../eth/rtl/verilog/TECH/xilinx
--y ../../eth/rtl/verilog/RMON
--y ../../eth
--y ../../eth/bench/verilog
++incdir+../eth/rtl/verilog
+-y ../eth/rtl/verilog
+-y ../eth/rtl/verilog/MAC_tx
+-y ../eth/rtl/verilog/MAC_rx
+-y ../eth/rtl/verilog/miim
+-y ../eth/rtl/verilog/TECH
+-y ../eth/rtl/verilog/TECH/xilinx
+-y ../eth/rtl/verilog/RMON
+-y ../eth
+-y ../eth/bench/verilog
 
 # Ethernet Models
--y ../../eth/bench/verilog
+-y ../eth/bench/verilog