[Commit-gnuradio] r7269 - in usrp2/trunk/fpga: timing top/single_u2_sim top/u2_basic

[matt]

Author: matt
Date: 2007-12-26 12:55:44 -0700 (Wed, 26 Dec 2007)
New Revision: 7269

Modified:
   usrp2/trunk/fpga/timing/time_receiver.v
   usrp2/trunk/fpga/timing/time_sender.v
   usrp2/trunk/fpga/timing/time_sync.v
   usrp2/trunk/fpga/top/single_u2_sim/single_u2_sim.v
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
make everything compile in its new place


Modified: usrp2/trunk/fpga/timing/time_receiver.v
===================================================================
--- usrp2/trunk/fpga/timing/time_receiver.v     2007-12-26 19:40:28 UTC (rev 
7268)
+++ usrp2/trunk/fpga/timing/time_receiver.v     2007-12-26 19:55:44 UTC (rev 
7269)
@@ -1,7 +1,7 @@
 
 module time_receiver
   (input clk, input rst,
-   output reg [31:0] master_clock,
+   output reg [31:0] master_time,
    output reg sync_rcvd,
    input exp_pps_in);
 
@@ -91,17 +91,17 @@
    always @(posedge clk)
      if(rst)
        begin
-         master_clock <= 0;
+         master_time <= 0;
          sync_rcvd <= 0;
        end
      else if(complete_word & (state == STATE_T3))
        begin
-         master_clock <= {clock_a, clock_b, clock_c, dataout_reg[7:0]};
+         master_time <= {clock_a, clock_b, clock_c, dataout_reg[7:0]};
          sync_rcvd <= 1;
        end
      else
        begin
-         master_clock <= master_clock + 1;
+         master_time <= master_time + 1;
          sync_rcvd <= 0;
        end
 endmodule // time_sender

Modified: usrp2/trunk/fpga/timing/time_sender.v
===================================================================
--- usrp2/trunk/fpga/timing/time_sender.v       2007-12-26 19:40:28 UTC (rev 
7268)
+++ usrp2/trunk/fpga/timing/time_sender.v       2007-12-26 19:55:44 UTC (rev 
7269)
@@ -2,7 +2,7 @@
 
 module time_sender
   (input clk, input rst,
-   input [31:0] master_clock,
+   input [31:0] master_time,
    input send_sync,
    output exp_pps_out);
 
@@ -11,7 +11,7 @@
    wire [9:0] dataout;
    reg [9:0] dataout_reg;
    reg              disp_reg;
-   wire      disp;
+   wire      disp, new_word;
    
    encode_8b10b encode_8b10b 
      (.datain({k,datain}),.dispin(disp_reg),
@@ -56,13 +56,13 @@
    localparam COMMA = 8'hBC;
    localparam HEAD = 8'h3C;
 
-   reg [31:0] master_clock_reg;
+   reg [31:0] master_time_reg;
    
    always @(posedge clk)
      if(rst)
-       master_clock_reg <= 0;
+       master_time_reg <= 0;
      else if(send_sync)
-       master_clock_reg <= master_clock;
+       master_time_reg <= master_time;
    
    always @(posedge clk)
      if(rst)
@@ -84,22 +84,22 @@
             end
           SEND_T0 :
             begin
-               {k,datain} <= {1'b0, master_clock_reg[31:24] };
+               {k,datain} <= {1'b0, master_time_reg[31:24] };
                state <= SEND_T1;
             end
           SEND_T1 :
             begin
-               {k,datain} <= {1'b0, master_clock_reg[23:16]};
+               {k,datain} <= {1'b0, master_time_reg[23:16]};
                state <= SEND_T2;
             end
           SEND_T2 :
             begin
-               {k,datain} <= {1'b0, master_clock_reg[15:8]};
+               {k,datain} <= {1'b0, master_time_reg[15:8]};
                state <= SEND_T3;
             end
           SEND_T3 :
             begin
-               {k,datain} <= {1'b0, master_clock_reg[7:0]};
+               {k,datain} <= {1'b0, master_time_reg[7:0]};
                state <= SEND_IDLE;
             end
           default :

Modified: usrp2/trunk/fpga/timing/time_sync.v
===================================================================
--- usrp2/trunk/fpga/timing/time_sync.v 2007-12-26 19:40:28 UTC (rev 7268)
+++ usrp2/trunk/fpga/timing/time_sync.v 2007-12-26 19:55:44 UTC (rev 7269)
@@ -5,11 +5,13 @@
    input cyc_i, input stb_i, input [2:0] adr_i,
    input we_i, input [31:0] dat_i, output [31:0] dat_o, output ack_o,
    input sys_clk_i, output [31:0] master_time_o,
-   input pps_in, input exp_pps_in, output reg exp_pps_out,
+   input pps_in, input exp_pps_in, output exp_pps_out,
    output int_o );
 
    // Generate Internal master time if we are the master
    reg [31:0] master_time;
+   wire [31:0] master_time_rcvd;
+
    always @(posedge sys_clk_i)
      if(rst_i)
        master_time <= 0;
@@ -17,17 +19,19 @@
        master_time <= master_time + 1;
    assign     master_time_o = master_time;
 
+   wire       send_sync, sync_rcvd;
+   
    time_sender time_sender
-     (.clk(clk),.rst(rst),
-      .master_clock(master_clock),
+     (.clk(sys_clk_i),.rst(rst_i),
+      .master_time(master_time),
       .send_sync(send_sync),
-      .exp_pps_out(exp_pps) );
+      .exp_pps_out(exp_pps_out) );
 
    time_receiver time_receiver
-     (.clk(clk),.rst(rst),
-      .master_clock(master_clock_rcv),
+     (.clk(sys_clk_i),.rst(rst_i),
+      .master_time(master_time_rcvd),
       .sync_rcvd(sync_rcvd),
-      .exp_pps_in(exp_pps) );
+      .exp_pps_in(exp_pps_in) );
 
 
    
@@ -37,6 +41,7 @@
    wire       pps_free_run;
    reg               pps_int_enable;
    reg               exp_pps_in_decoded;
+   wire       pps_ext, pps_internal;
    
    assign     ack_o = stb_i;
 
@@ -87,13 +92,6 @@
        exp_pps_in_decoded <= (exp_pps_in_d1 == exp_pps_in);
      end
    
-   // Encode Expansion PPS Output
-   always @(posedge sys_clk_i)
-     if(rst_i)
-       exp_pps_out <= 0;
-     else if(~pps_internal)
-       exp_pps_out <= ~exp_pps_out;
-
    // Properly Latch and edge detect External PPS input
    always @(posedge sys_clk_i)
      begin

Modified: usrp2/trunk/fpga/top/single_u2_sim/single_u2_sim.v
===================================================================
--- usrp2/trunk/fpga/top/single_u2_sim/single_u2_sim.v  2007-12-26 19:40:28 UTC 
(rev 7268)
+++ usrp2/trunk/fpga/top/single_u2_sim/single_u2_sim.v  2007-12-26 19:55:44 UTC 
(rev 7269)
@@ -158,8 +158,8 @@
    initial begin
       @(negedge cpld_done);
       @(posedge cpld_done);
-      $dumpfile("u2_sim_top.lxt");
-      $dumpvars(0,u2_sim_top);
+      $dumpfile("single_u2_sim.lxt");
+      $dumpvars(0,single_u2_sim);
    end
 
    initial #10000000 $finish;

Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-12-26 19:40:28 UTC (rev 
7268)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2007-12-26 19:55:44 UTC (rev 
7269)
@@ -131,7 +131,7 @@
    wire        ram_loader_rst, wb_rst, dsp_rst;
 
    wire [31:0]         status, status_b0, status_b1, status_b2, status_b3, 
status_b4, status_b5, status_b6, status_b7;
-   wire        bus_error, spi_int, i2c_int, timer_int, buffer_int, proc_int, 
overrun, underrun, uart_int;
+   wire        bus_error, spi_int, i2c_int, pps_int, timer_int, buffer_int, 
proc_int, overrun, underrun, uart_int;
 
    wire [31:0]         debug_gpio_0, debug_gpio_1;
    wire [31:0]         debug_rx, debug_rx_1, debug_rx_2;
@@ -148,15 +148,16 @@
    wire [dw-1:0] m0_dat_o, m1_dat_o, m0_dat_i, m1_dat_i;
    wire [dw-1:0] s0_dat_o, s1_dat_o, s0_dat_i, s1_dat_i, s2_dat_o, s3_dat_o, 
s2_dat_i, s3_dat_i,
                 s4_dat_o, s5_dat_o, s4_dat_i, s5_dat_i, s6_dat_o, s7_dat_o, 
s6_dat_i, s7_dat_i,
-                s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, 
s11_dat_i, s11_dat_o;
-   wire [aw-1:0] 
m0_adr,m1_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr;
-   wire [sw-1:0] 
m0_sel,m1_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel;
-   wire         
m0_ack,m1_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack;
-   wire         
m0_stb,m1_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb;
-   wire         
m0_cyc,m1_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc;
-   wire         
m0_err,m1_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err;
-   wire         
m0_rty,m1_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty;
-   wire         
m0_we,m1_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we;
+                s8_dat_o, s9_dat_o, s8_dat_i, s9_dat_i, s10_dat_o, s10_dat_i, 
s11_dat_i, s11_dat_o,
+                s12_dat_i, s12_dat_o;
+   wire [aw-1:0] 
m0_adr,m1_adr,s0_adr,s1_adr,s2_adr,s3_adr,s4_adr,s5_adr,s6_adr,s7_adr,s8_adr,s9_adr,s10_adr,s11_adr,s12_adr;
+   wire [sw-1:0] 
m0_sel,m1_sel,s0_sel,s1_sel,s2_sel,s3_sel,s4_sel,s5_sel,s6_sel,s7_sel,s8_sel,s9_sel,s10_sel,s11_sel,s12_sel;
+   wire         
m0_ack,m1_ack,s0_ack,s1_ack,s2_ack,s3_ack,s4_ack,s5_ack,s6_ack,s7_ack,s8_ack,s9_ack,s10_ack,s11_ack,s12_ack;
+   wire         
m0_stb,m1_stb,s0_stb,s1_stb,s2_stb,s3_stb,s4_stb,s5_stb,s6_stb,s7_stb,s8_stb,s9_stb,s10_stb,s11_stb,s12_stb;
+   wire         
m0_cyc,m1_cyc,s0_cyc,s1_cyc,s2_cyc,s3_cyc,s4_cyc,s5_cyc,s6_cyc,s7_cyc,s8_cyc,s9_cyc,s10_cyc,s11_cyc,s12_cyc;
+   wire         
m0_err,m1_err,s0_err,s1_err,s2_err,s3_err,s4_err,s5_err,s6_err,s7_err,s8_err,s9_err,s10_err,s11_err,s12_err;
+   wire         
m0_rty,m1_rty,s0_rty,s1_rty,s2_rty,s3_rty,s4_rty,s5_rty,s6_rty,s7_rty,s8_rty,s9_rty,s10_rty,s11_rty,s12_rty;
+   wire         
m0_we,m1_we,s0_we,s1_we,s2_we,s3_we,s4_we,s5_we,s6_we,s7_we,s8_we,s9_we,s10_we,s11_we,s12_we;
    
    wb_1master #(.s0_addr_w(2),.s0_addr(2'b00),.s1_addr_w(2),.s1_addr(2'b01),
                
.s215_addr_w(6),.s2_addr(6'b100000),.s3_addr(6'b100100),.s4_addr(6'b101000),
@@ -191,7 +192,8 @@
       
.s10_dat_i(s10_dat_i),.s10_ack_i(s10_ack),.s10_err_i(s10_err),.s10_rty_i(s10_rty),
       
.s11_dat_o(s11_dat_o),.s11_adr_o(s11_adr),.s11_sel_o(s11_sel),.s11_we_o(s11_we),.s11_cyc_o(s11_cyc),.s11_stb_o(s11_stb),
       
.s11_dat_i(s11_dat_i),.s11_ack_i(s11_ack),.s11_err_i(s11_err),.s11_rty_i(s11_rty),
-      .s12_dat_i(0),.s12_ack_i(0),.s12_err_i(0),.s12_rty_i(0),
+      
.s12_dat_o(s12_dat_o),.s12_adr_o(s12_adr),.s12_sel_o(s12_sel),.s12_we_o(s12_we),.s12_cyc_o(s12_cyc),.s12_stb_o(s12_stb),
+      
.s12_dat_i(s12_dat_i),.s12_ack_i(s12_ack),.s12_err_i(s12_err),.s12_rty_i(s12_rty),
       .s13_dat_i(0),.s13_ack_i(0),.s13_err_i(0),.s13_rty_i(0),
       .s14_dat_i(0),.s14_ack_i(0),.s14_err_i(0),.s14_rty_i(0),
       .s15_dat_i(0),.s15_ack_i(0),.s15_err_i(0),.s15_rty_i(0)  );
@@ -433,7 +435,8 @@
    // /////////////////////////////////////////////////////////////////////////
    // Interrupt Controller, Slave #8
 
-   wire [7:0]   irq = 
{uart_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int};
+   //wire [7:0]         irq = 
{uart_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int};
+   wire [7:0]   irq = 
{pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int};
    simple_pic simple_pic
      
(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
       
.we_i(s8_we),.dat_i(s8_dat_o[7:0]),.dat_o(s8_dat_i[7:0]),.ack_o(s8_ack),.int_o(proc_int),
@@ -448,17 +451,12 @@
    wire [31:0]          master_time;
    timer timer
      (.wb_clk_i(wb_clk),.rst_i(wb_rst),
-      .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[2:0]),
+      .cyc_i(s9_cyc),.stb_i(s9_stb),.adr_i(s9_adr[4:2]),
       .we_i(s9_we),.dat_i(s9_dat_o),.dat_o(s9_dat_i),.ack_o(s9_ack),
-      .sys_clk_i(dsp_clk),.master_time_o(master_time),.int_o(timer_int) );
+      .sys_clk_i(dsp_clk),.master_time_i(master_time),.int_o(timer_int) );
    assign       s9_err = 0;
    assign       s9_rty = 0;
-   
-   pps pps
-     (.clk(dsp_clk),.rst(dsp_rst),
-      .pps_in(pps_in),.exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
-      .master_time(master_time) );
-   
+
    // /////////////////////////////////////////////////////////////////////////
    // UART, Slave #10
 
@@ -486,6 +484,19 @@
    assign       s11_err = 0;
    assign       s11_rty = 0;
    
+   // 
//////////////////////////////////////////////////////////////////////////
+   // Time Sync, Slave #12 
+
+   time_sync time_sync
+     (.wb_clk_i(wb_clk),.rst_i(wb_rst),
+      .cyc_i(s12_cyc),.stb_i(s12_stb),.adr_i(s12_adr[4:2]),
+      .we_i(s12_we),.dat_i(s12_dat_o),.dat_o(s12_dat_i),.ack_o(s12_ack),
+      .sys_clk_i(dsp_clk),.master_time_o(master_time),
+      .pps_in(pps_in),.exp_pps_in(exp_pps_in),.exp_pps_out(exp_pps_out),
+      .int_o(pps_int) );
+   assign       s12_err = 0;
+   assign       s12_rty = 0;
+   
    // /////////////////////////////////////////////////////////////////////////
    // DSP