[Commit-gnuradio] r7264 - in usrp2/trunk/fpga: . testbench top/u2_sim

[matt]

Author: matt
Date: 2007-12-26 12:23:36 -0700 (Wed, 26 Dec 2007)
New Revision: 7264

Added:
   usrp2/trunk/fpga/testbench/
   usrp2/trunk/fpga/testbench/Makefile
   usrp2/trunk/fpga/testbench/cmdfile
Removed:
   usrp2/trunk/fpga/top/u2_sim/Makefile
   usrp2/trunk/fpga/top/u2_sim/cmdfile
Log:
moving stuff around


Copied: usrp2/trunk/fpga/testbench/Makefile (from rev 7263, 
usrp2/trunk/fpga/top/u2_sim/Makefile)
===================================================================
--- usrp2/trunk/fpga/testbench/Makefile                         (rev 0)
+++ usrp2/trunk/fpga/testbench/Makefile 2007-12-26 19:23:36 UTC (rev 7264)
@@ -0,0 +1,7 @@
+all: u2_sim
+
+u2_sim:        
+       iverilog -Wimplicit -Wportbind -c cmdfile u2_sim_top.v -o u2_sim
+
+clean:
+       rm -f u2_sim *.vcd

Copied: usrp2/trunk/fpga/testbench/cmdfile (from rev 7263, 
usrp2/trunk/fpga/top/u2_sim/cmdfile)
===================================================================
--- usrp2/trunk/fpga/testbench/cmdfile                          (rev 0)
+++ usrp2/trunk/fpga/testbench/cmdfile  2007-12-26 19:23:36 UTC (rev 7264)
@@ -0,0 +1,38 @@
+# My stuff
+-y .
+-y ../u2_basic
+-y ../../control_lib
+-y ../../serdes
+-y ../../sdr_lib
+
+# Models
+-y ../../models
+-y ../../models/CY7C1356C
+
+# Open Cores
+-y ../../opencores/spi/rtl/verilog
++incdir+../../opencores/spi/rtl/verilog
+-y ../../opencores/wb_conbus/rtl/verilog
++incdir+../../opencores/wb_conbus/rtl/verilog
+-y ../../opencores/i2c/rtl/verilog
++incdir+../../opencores/i2c/rtl/verilog
+-y ../../opencores/aemb/rtl/verilog
+-y ../../opencores/simple_gpio/rtl
+-y ../../opencores/simple_pic/rtl
+-y ../../opencores/uart16550/rtl/verilog
++incdir+../../opencores/uart16550/rtl/verilog
+
+# Ethernet
++incdir+../../eth/rtl/verilog
+-y ../../eth/rtl/verilog
+-y ../../eth/rtl/verilog/MAC_tx
+-y ../../eth/rtl/verilog/MAC_rx
+-y ../../eth/rtl/verilog/miim
+-y ../../eth/rtl/verilog/TECH
+-y ../../eth/rtl/verilog/TECH/xilinx
+-y ../../eth/rtl/verilog/RMON
+-y ../../eth
+-y ../../eth/bench/verilog
+
+# Ethernet Models
+-y ../../eth/bench/verilog

Deleted: usrp2/trunk/fpga/top/u2_sim/Makefile

Deleted: usrp2/trunk/fpga/top/u2_sim/cmdfile