[Commit-gnuradio] r7263 - usrp2/trunk/fpga/timing

[matt]

Author: matt
Date: 2007-12-26 01:49:04 -0700 (Wed, 26 Dec 2007)
New Revision: 7263

Added:
   usrp2/trunk/fpga/timing/time_receiver.v
   usrp2/trunk/fpga/timing/time_sender.v
   usrp2/trunk/fpga/timing/time_transfer_tb.v
Modified:
   usrp2/trunk/fpga/timing/
Log:
first cut at a time transfer system



Property changes on: usrp2/trunk/fpga/timing
___________________________________________________________________
Name: svn:ignore
   + a.out
*.vcd


Added: usrp2/trunk/fpga/timing/time_receiver.v
===================================================================
--- usrp2/trunk/fpga/timing/time_receiver.v                             (rev 0)
+++ usrp2/trunk/fpga/timing/time_receiver.v     2007-12-26 08:49:04 UTC (rev 
7263)
@@ -0,0 +1,107 @@
+
+module time_receiver
+  (input clk, input rst,
+   output reg [31:0] master_clock,
+   output reg pps,
+   input exp_pps_in);
+
+   wire       code_err, disp_err, dispout, complete_word;
+   reg               disp_reg;
+   reg [9:0]  shiftreg;
+   reg [3:0]  bit_count;
+   wire [8:0] dataout;
+   reg [8:0]  dataout_reg;
+             
+   always @(posedge clk)
+     shiftreg <= {exp_pps_in, shiftreg[9:1]};
+
+   localparam COMMA_0 = 10'h283;
+   localparam COMMA_1 = 10'h17c;
+   
+   wire       found_comma = (shiftreg == COMMA_0) | (shiftreg == COMMA_1);
+   wire       set_disp = (shiftreg == COMMA_1);
+
+   always @(posedge clk)
+     if(rst)
+       bit_count <= 0;
+     else if(found_comma | complete_word)
+       bit_count <= 0;
+     else 
+       bit_count <= bit_count + 1;
+   assign     complete_word = (bit_count == 9);
+
+   always @(posedge clk)
+     if(set_disp)
+       disp_reg <= 1;
+     else if(complete_word)
+       disp_reg <= dispout;
+
+   always @(posedge clk)
+     if(complete_word)
+       dataout_reg <= dataout;
+     
+   decode_8b10b decode_8b10b 
+     (.datain(shiftreg),.dispin(disp_reg),
+      .dataout(dataout),.dispout(dispout),
+      .code_err(code_err),.disp_err(disp_err) );
+
+   reg               error;
+   always @(posedge clk)
+     if(complete_word)
+       error <= code_err | disp_err;
+   
+   localparam STATE_IDLE = 0;
+   localparam STATE_T0 = 1;
+   localparam STATE_T1 = 2;
+   localparam STATE_T2 = 3;
+   localparam STATE_T3 = 4;
+   
+   localparam HEAD = 9'h13c;   
+
+   reg [7:0]  clock_a, clock_b, clock_c;
+   reg [2:0]  state;
+   
+   always @(posedge clk)
+     if(rst)
+       state <= STATE_IDLE;
+     else if(complete_word)
+       case(state)
+        STATE_IDLE :
+          if(dataout_reg == HEAD)
+            state <= STATE_T0;
+        STATE_T0 :
+          begin
+             clock_a <= dataout_reg[7:0];
+             state <= STATE_T1;
+          end
+        STATE_T1 :
+          begin
+             clock_b <= dataout_reg[7:0];
+             state <= STATE_T2;
+          end
+        STATE_T2 :
+          begin
+             clock_c <= dataout_reg[7:0];
+             state <= STATE_T3;
+          end
+        STATE_T3 :
+          state <= STATE_IDLE;
+       endcase // case(state)
+
+   always @(posedge clk)
+     if(rst)
+       begin
+         master_clock <= 0;
+         pps <= 0;
+       end
+     else if(complete_word & (state == STATE_T3))
+       begin
+         pps <= 1;
+         master_clock <= {clock_a, clock_b, clock_c, dataout_reg[7:0]};
+       end
+     else
+       begin
+         master_clock <= master_clock + 1;
+         pps <= 0;
+       end
+endmodule // time_sender

Added: usrp2/trunk/fpga/timing/time_sender.v
===================================================================
--- usrp2/trunk/fpga/timing/time_sender.v                               (rev 0)
+++ usrp2/trunk/fpga/timing/time_sender.v       2007-12-26 08:49:04 UTC (rev 
7263)
@@ -0,0 +1,110 @@
+
+
+module time_sender
+  (input clk, input rst,
+   input [31:0] master_clock,
+   input pps,
+   output exp_pps_out);
+
+   reg [7:0] datain;
+   reg              k;
+   wire [9:0] dataout;
+   reg [9:0] dataout_reg;
+   reg              disp_reg;
+   wire      disp;
+   
+   encode_8b10b encode_8b10b 
+     (.datain({k,datain}),.dispin(disp_reg),
+      .dataout(dataout),.dispout(disp));
+
+   assign    exp_pps_out = dataout_reg[0];
+
+   always @(posedge clk)
+     if(rst)
+       disp_reg <= 0;
+     else if(new_word)
+       disp_reg <= disp;
+   
+   always @(posedge clk)
+     if(rst)
+       dataout_reg <= 0;
+     else if(new_word)
+       dataout_reg <= dataout;
+     else
+       dataout_reg <= {1'b0,dataout_reg[9:1]};
+   
+   reg [4:0] state;
+   reg [3:0] bit_count;
+
+   assign    new_word = (bit_count == 9);
+   
+   always @(posedge clk)
+     if(rst)
+       bit_count <= 0;
+     else if(new_word | pps)
+       bit_count <= 0;
+     else
+       bit_count <= bit_count + 1;
+
+   localparam SEND_IDLE = 0;
+   localparam SEND_HEAD = 1;
+   localparam SEND_T0 = 2;
+   localparam SEND_T1 = 3;
+   localparam SEND_T2 = 4;
+   localparam SEND_T3 = 5;
+
+   localparam COMMA = 8'hBC;
+   localparam HEAD = 8'h3C;
+
+   reg [31:0] master_clock_reg;
+   
+   always @(posedge clk)
+     if(rst)
+       master_clock_reg <= 0;
+     else if(pps)
+       master_clock_reg <= master_clock;
+   
+   always @(posedge clk)
+     if(rst)
+       begin
+         {k,datain} <= 0;
+         state <= SEND_IDLE;
+       end
+     else
+       if(pps)
+        state <= SEND_HEAD;
+       else if(new_word)
+        case(state)
+          SEND_IDLE :
+            {k,datain} <= {1'b1,COMMA};
+          SEND_HEAD :
+            begin
+               {k,datain} <= {1'b1, HEAD};
+               state <= SEND_T0;
+            end
+          SEND_T0 :
+            begin
+               {k,datain} <= {1'b0, master_clock_reg[31:24] };
+               state <= SEND_T1;
+            end
+          SEND_T1 :
+            begin
+               {k,datain} <= {1'b0, master_clock_reg[23:16]};
+               state <= SEND_T2;
+            end
+          SEND_T2 :
+            begin
+               {k,datain} <= {1'b0, master_clock_reg[15:8]};
+               state <= SEND_T3;
+            end
+          SEND_T3 :
+            begin
+               {k,datain} <= {1'b0, master_clock_reg[7:0]};
+               state <= SEND_IDLE;
+            end
+          default :
+            state <= SEND_IDLE;
+        endcase // case(state)
+   
+   
+endmodule // time_sender

Added: usrp2/trunk/fpga/timing/time_transfer_tb.v
===================================================================
--- usrp2/trunk/fpga/timing/time_transfer_tb.v                          (rev 0)
+++ usrp2/trunk/fpga/timing/time_transfer_tb.v  2007-12-26 08:49:04 UTC (rev 
7263)
@@ -0,0 +1,50 @@
+
+`timescale 1ns / 1ps
+
+module time_transfer_tb();
+
+   reg clk = 0, rst = 1;
+   always #5 clk = ~clk;
+   
+   initial 
+     begin
+       @(negedge clk);
+       @(negedge clk);
+       rst <= 0;
+     end
+
+   initial $dumpfile("time_transfer_tb.vcd");
+   initial $dumpvars(0,time_transfer_tb);
+   
+   initial #100000000 $finish;
+
+   wire exp_pps, pps, pps_rcv;
+   wire [31:0] master_clock_rcv;
+   reg [31:0]  master_clock = 0;
+   reg [31:0]  counter = 0;
+
+   localparam  PPS_PERIOD = 109;
+   always @(posedge clk)
+     if(counter == PPS_PERIOD)
+       counter <= 0;
+     else
+       counter <= counter + 1;
+   assign      pps = (counter == (PPS_PERIOD-1));
+   
+   always @(posedge clk)
+     master_clock <= master_clock + 1;
+   
+   time_sender time_sender
+     (.clk(clk),.rst(rst),
+      .master_clock(master_clock),
+      .pps(pps),
+      .exp_pps_out(exp_pps) );
+
+   time_receiver time_receiver
+     (.clk(clk),.rst(rst),
+      .master_clock(master_clock_rcv),
+      .pps(pps_rcv),
+      .exp_pps_in(exp_pps) );
+
+   wire [31:0] delta = master_clock - master_clock_rcv;
+endmodule // time_transfer_tb