[Commit-gnuradio] r7221 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2007-12-17 17:49:58 -0700 (Mon, 17 Dec 2007)
New Revision: 7221

Added:
   usrp2/trunk/fpga/sdr_lib/hb_decim.v
Log:
beginnings of a xilinx-optimized halfband decimator


Added: usrp2/trunk/fpga/sdr_lib/hb_decim.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/hb_decim.v                         (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/hb_decim.v 2007-12-18 00:49:58 UTC (rev 7221)
@@ -0,0 +1,74 @@
+
+`define SET_COEFF  124
+
+module hb_decim
+  #(parameter SWIDTH = 16,
+    parameter CWIDTH = 16,
+    parameter TWIDTH = 16,
+    parameter ACC_WIDTH = 40)
+    (input clk, input rst,
+     input set_stb, input [7:0] set_addr, input [31:0] set_data,
+     input [SWIDTH-1:0] sample_in,
+     input strobe_in,
+     output [SWIDTH-1:0] sample_out.
+     output strobe_out 
+     );
+
+   reg [3:0] even_addr, odd_addr_a, odd_addr_b;
+   genvar    i;
+   
+   wire [SWIDTH-1:0] cascade, even_sample, odd_sample_a, odd_sample_b, odd_sum;
+   wire [SWIDTH:0]   odd_sum = {odd_sample_a[SWIDTH-1],odd_sample_a} 
+                    + {odd_sample_b[SWIDTH-1],odd_sample_b};
+
+   wire [CWIDTH-1:0] odd_coeff, even_coeff;
+   wire             write_coeff = (set_addr == `SET_COEFF) & set_stb;
+   wire             write_table = (set_addr == `SET_TABLE) & set_stb;
+
+   wire [TWIDTH-1:0] control_word;
+   
+   generate
+      for (i=0;i<TWIDTH;i=i+1)
+       begin : gen_table_srl
+          SRLC16E
+            srlc_table(.Q(control_word),.Q15(),
+                       .A0(phase[0]),.A1(phase[1]),.A2(phase[2]),.A3(phase[3]),
+                       .CE(write_table),.CLK(clk),.D(set_data[i]));
+       end
+   endgenerate
+              
+   generate
+      for (i=0;i<CWDITH;i=i+1)
+       begin : gen_coeff_srl
+          SRLC16E
+            srlc_coeff(.Q(odd_coeff[i]),.Q15(even_coeff[i]),
+                       
.A0(coeff_addr[0]),.A1(coeff_addr[1]),.A2(coeff_addr[2]),.A3(coeff_addr[3]),
+                       .CE(write_coeff),.CLK(clk),.D(set_data[i]));
+       end
+   endgenerate
+   
+   generate
+      for (i=0;i<SWIDTH;i=i+1)
+       begin : gen_sample_srls
+          SRL16E
+            srl_even(.Q(even_sample[i]),
+                     
.A0(even_addr[0]),.A1(even_addr[1]),.A2(even_addr[2]),.A3(even_addr[3]),
+                     .CE(write_even),.CLK(clk),.D(sample_in[i]));
+          SRLC16E
+            srlc_odd_a(.Q(odd_sample_a[i]),.Q15(cascade[i])
+                       
.A0(odd_addr_a[0]),.A1(odd_addr_a[1]),.A2(odd_addr_a[2]),.A3(odd_addr_a[3]),
+                       .CE(write_odd),.CLK(clk),.D(sample_in[i]));
+          SRL16E
+            srl_odd_b(.Q(even_sample[i]),
+                      
.A0(odd_addr_b[0]),.A1(odd_addr_b[1]),.A2(odd_addr_b[2]),.A3(odd_addr_b[3]),
+                      .CE(write_odd),.CLK(clk),.D(cascade[i]));
+       end
+   endgenerate
+
+   reg [
+   reg [3:0] phase;
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+       phase < = 0
+endmodule // hb_decim