[Commit-gnuradio] r7220 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2007-12-17 17:49:36 -0700 (Mon, 17 Dec 2007)
New Revision: 7220

Modified:
   usrp2/trunk/fpga/sdr_lib/cic_dec_shifter.v
   usrp2/trunk/fpga/sdr_lib/cic_decim.v
Log:
registered the shifter to help timing


Modified: usrp2/trunk/fpga/sdr_lib/cic_dec_shifter.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/cic_dec_shifter.v  2007-12-17 17:54:12 UTC (rev 
7219)
+++ usrp2/trunk/fpga/sdr_lib/cic_dec_shifter.v  2007-12-18 00:49:36 UTC (rev 
7220)
@@ -23,10 +23,11 @@
 // NOTE   This only works for N=4, max decim rate of 128
 // NOTE   signal "rate" is ONE LESS THAN the actual rate
 
-module cic_dec_shifter(rate,signal_in,signal_out);
+module cic_dec_shifter(clock,rate,signal_in,signal_out);
    parameter bw = 16;
    parameter maxbitgain = 28;
-   
+
+   input     clock;
    input [7:0] rate;
    input       wire [bw+maxbitgain-1:0] signal_in;
    output      reg [bw-1:0] signal_out;
@@ -70,30 +71,30 @@
    // We should be able to do this, but can't ....
    // assign     signal_out = signal_in[shift+bw-1:shift];
    
-   always @*
+   always @(posedge clock)
      case(shift)
-       5'd8  : signal_out = signal_in[8+bw-1:8];
-       5'd10 : signal_out = signal_in[10+bw-1:10];
-       5'd11 : signal_out = signal_in[11+bw-1:11];
-       5'd12 : signal_out = signal_in[12+bw-1:12];
-       5'd13 : signal_out = signal_in[13+bw-1:13];
-       5'd14 : signal_out = signal_in[14+bw-1:14];
-       5'd15 : signal_out = signal_in[15+bw-1:15];
-       5'd16 : signal_out = signal_in[16+bw-1:16];
-       5'd17 : signal_out = signal_in[17+bw-1:17];
-       5'd18 : signal_out = signal_in[18+bw-1:18];
-       5'd19 : signal_out = signal_in[19+bw-1:19];
-       5'd20 : signal_out = signal_in[20+bw-1:20];
-       5'd21 : signal_out = signal_in[21+bw-1:21];
-       5'd22 : signal_out = signal_in[22+bw-1:22];
-       5'd23 : signal_out = signal_in[23+bw-1:23];
-       5'd24 : signal_out = signal_in[24+bw-1:24];
-       5'd25 : signal_out = signal_in[25+bw-1:25];
-       5'd26 : signal_out = signal_in[26+bw-1:26];
-       5'd27 : signal_out = signal_in[27+bw-1:27];
-       5'd28 : signal_out = signal_in[28+bw-1:28];
+       5'd8  : signal_out <= signal_in[8+bw-1:8];
+       5'd10 : signal_out <= signal_in[10+bw-1:10];
+       5'd11 : signal_out <= signal_in[11+bw-1:11];
+       5'd12 : signal_out <= signal_in[12+bw-1:12];
+       5'd13 : signal_out <= signal_in[13+bw-1:13];
+       5'd14 : signal_out <= signal_in[14+bw-1:14];
+       5'd15 : signal_out <= signal_in[15+bw-1:15];
+       5'd16 : signal_out <= signal_in[16+bw-1:16];
+       5'd17 : signal_out <= signal_in[17+bw-1:17];
+       5'd18 : signal_out <= signal_in[18+bw-1:18];
+       5'd19 : signal_out <= signal_in[19+bw-1:19];
+       5'd20 : signal_out <= signal_in[20+bw-1:20];
+       5'd21 : signal_out <= signal_in[21+bw-1:21];
+       5'd22 : signal_out <= signal_in[22+bw-1:22];
+       5'd23 : signal_out <= signal_in[23+bw-1:23];
+       5'd24 : signal_out <= signal_in[24+bw-1:24];
+       5'd25 : signal_out <= signal_in[25+bw-1:25];
+       5'd26 : signal_out <= signal_in[26+bw-1:26];
+       5'd27 : signal_out <= signal_in[27+bw-1:27];
+       5'd28 : signal_out <= signal_in[28+bw-1:28];
        
-       default : signal_out = signal_in[28+bw-1:28];
+       default : signal_out <= signal_in[28+bw-1:28];
      endcase // case(shift)
 
 endmodule // cic_dec_shifter

Modified: usrp2/trunk/fpga/sdr_lib/cic_decim.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/cic_decim.v        2007-12-17 17:54:12 UTC (rev 
7219)
+++ usrp2/trunk/fpga/sdr_lib/cic_decim.v        2007-12-18 00:49:36 UTC (rev 
7220)
@@ -80,6 +80,6 @@
    wire [bw+maxbitgain-1:0] signal_out_unnorm = pipeline[N-1];
    
    cic_dec_shifter #(bw)
-     cic_dec_shifter(rate,signal_out_unnorm,signal_out);
+     cic_dec_shifter(clock,rate,signal_out_unnorm,signal_out);
    
 endmodule // cic_decim