[Commit-gnuradio] r7197 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2007-12-15 16:00:04 -0700 (Sat, 15 Dec 2007)
New Revision: 7197

Modified:
   usrp2/trunk/fpga/control_lib/fifo_tb.v
Log:
added in new kinds of fifos.  this tb should be expanded


Modified: usrp2/trunk/fpga/control_lib/fifo_tb.v
===================================================================
--- usrp2/trunk/fpga/control_lib/fifo_tb.v      2007-12-15 22:42:01 UTC (rev 
7196)
+++ usrp2/trunk/fpga/control_lib/fifo_tb.v      2007-12-15 23:00:04 UTC (rev 
7197)
@@ -2,19 +2,31 @@
    
    reg clk, rst;
    wire short_full, short_empty, long_full, long_empty;
+   wire casc_full, casc_empty, casc2_full, casc2_empty;
    reg         read, write;
    
    wire [7:0] short_do, long_do;
+   wire [7:0] casc_do, casc2_do;
    reg [7:0]  di;
+
+   reg               clear = 0;
    
    shortfifo #(.WIDTH(8)) shortfifo
-     (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),
+     (.clk(clk),.rst(rst),.datain(di),.dataout(short_do),.clear(clear),
       .read(read),.write(write),.full(short_full),.empty(short_empty));
    
    longfifo #(.WIDTH(8), .SIZE(4)) longfifo
-     (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),
+     (.clk(clk),.rst(rst),.datain(di),.dataout(long_do),.clear(clear),
       .read(read),.write(write),.full(long_full),.empty(long_empty));
    
+   cascadefifo #(.WIDTH(8), .SIZE(4)) cascadefifo
+     (.clk(clk),.rst(rst),.datain(di),.dataout(casc_do),.clear(clear),
+      .read(read),.write(write),.full(casc_full),.empty(casc_empty));
+   
+   cascadefifo2 #(.WIDTH(8), .SIZE(4)) cascadefifo2
+     (.clk(clk),.rst(rst),.datain(di),.dataout(casc2_do),.clear(clear),
+      .read(read),.write(write),.full(casc2_full),.empty(casc2_empty));
+   
    initial rst = 1;
    initial #1000 rst = 0;
    initial clk = 0;
@@ -51,10 +63,21 @@
        @(posedge clk);
        write <= 0;
        @(posedge clk);
+       @(posedge clk);
+       @(posedge clk);
+       @(posedge clk);
+       @(posedge clk);
+       @(posedge clk);
+       @(posedge clk);
+       @(posedge clk);
        read <= 1;
        @(posedge clk);
        read <= 0;
        @(posedge clk);
+       @(posedge clk);
+       @(posedge clk);
+       @(posedge clk);
+       @(posedge clk);
 
        repeat(10)
          begin
@@ -62,10 +85,16 @@
             @(posedge clk);
             write <= 0;
             @(posedge clk);
+            @(posedge clk);
+            @(posedge clk);
             read <= 1;
             @(posedge clk);
             read <= 0;
-            //@(posedge clk);
+            @(posedge clk);
+            @(posedge clk);
+            @(posedge clk);
+            @(posedge clk);
+            @(posedge clk);
          end // repeat (10)
        
        write <= 1;