[Commit-gnuradio] r7170 - in usrp2/trunk: firmware/lib fpga/models

[matt]

Author: matt
Date: 2007-12-14 01:21:25 -0700 (Fri, 14 Dec 2007)
New Revision: 7170

Modified:
   usrp2/trunk/firmware/lib/memory_map.h
   usrp2/trunk/fpga/models/adc_model.v
Log:
invert sense on controls


Modified: usrp2/trunk/firmware/lib/memory_map.h
===================================================================
--- usrp2/trunk/firmware/lib/memory_map.h       2007-12-14 07:32:17 UTC (rev 
7169)
+++ usrp2/trunk/firmware/lib/memory_map.h       2007-12-14 08:21:25 UTC (rev 
7170)
@@ -313,8 +313,8 @@
 #define SERDES_LOOPEN 2
 #define SERDES_RXEN   1
 
-#define        ADC_CTRL_ON     0x00
-#define        ADC_CTRL_OFF    0x0A
+#define        ADC_CTRL_ON     0x0F
+#define        ADC_CTRL_OFF    0x00
 
 #define output_regs ((output_regs_t *) MISC_OUTPUT_BASE)
 

Modified: usrp2/trunk/fpga/models/adc_model.v
===================================================================
--- usrp2/trunk/fpga/models/adc_model.v 2007-12-14 07:32:17 UTC (rev 7169)
+++ usrp2/trunk/fpga/models/adc_model.v 2007-12-14 08:21:25 UTC (rev 7170)
@@ -3,22 +3,23 @@
   (input clk, input rst,
    output [13:0] adc_a,
    output adc_ovf_a,
-   input adc_oen_a,
-   input adc_pdn_a,
+   input adc_on_a,
+   input adc_oe_a,
    output [13:0] adc_b,
    output adc_ovf_b,
-   input adc_oen_b,
-   input adc_pdn_b);
-
+   input adc_on_b,
+   input adc_oe_b
+   );
+   
    math_real math ( ) ;
 
    reg [13:0] adc_a_int = 0;
    reg [13:0] adc_b_int = 0;
    
-   assign     adc_a = (~adc_oen_a & ~adc_pdn_a) ? adc_a_int : 14'bz;
-   assign     adc_ovf_a = (~adc_oen_a & ~adc_pdn_a) ? 1'b0 : 1'bz;
-   assign     adc_b = (~adc_oen_b & ~adc_pdn_b) ? adc_b_int : 14'bz;
-   assign     adc_ovf_b = (~adc_oen_b & ~adc_pdn_b) ? 1'b0 : 1'bz;
+   assign     adc_a = adc_oe_a ? adc_a_int : 14'bz;
+   assign     adc_ovf_a = adc_oe_a ? 1'b0 : 1'bz;
+   assign     adc_b = adc_oe_b ? adc_b_int : 14'bz;
+   assign     adc_ovf_b = adc_oe_b ? 1'b0 : 1'bz;
    
    real phase = 0;
 
@@ -28,14 +29,15 @@
    real freq = 330000/sample_rate;     // 330 kHz
    
    always @(posedge clk)
-     if(~adc_pdn_a & ~adc_oen_a)
-       begin
+     begin
+       if(adc_on_a)
          adc_a_int <= 
$rtoi(math.round(math.sin(phase*math.MATH_2_PI)*(math.pow(2,13)-1))) ;
+       if(adc_on_b)
          adc_b_int <= 
$rtoi(math.round(math.cos(phase*math.MATH_2_PI)*(math.pow(2,13)-1))) ;
-         if(phase > 1)
-           phase <= phase + freq - 1;
-         else
-           phase <= phase + freq;
-       end
+       if(phase > 1)
+         phase <= phase + freq - 1;
+       else
+         phase <= phase + freq;
+     end
    
 endmodule // adc_model