[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] r7069 - usrp2/trunk/fpga/control_lib
From: |
matt |
Subject: |
[Commit-gnuradio] r7069 - usrp2/trunk/fpga/control_lib |
Date: |
Mon, 3 Dec 2007 23:51:35 -0700 (MST) |
Author: matt
Date: 2007-12-03 23:51:35 -0700 (Mon, 03 Dec 2007)
New Revision: 7069
Modified:
usrp2/trunk/fpga/control_lib/cascadefifo.v
usrp2/trunk/fpga/control_lib/cascadefifo2.v
usrp2/trunk/fpga/control_lib/longfifo.v
Log:
bring out signal to tell us how much space there is
Modified: usrp2/trunk/fpga/control_lib/cascadefifo.v
===================================================================
--- usrp2/trunk/fpga/control_lib/cascadefifo.v 2007-12-04 06:50:40 UTC (rev
7068)
+++ usrp2/trunk/fpga/control_lib/cascadefifo.v 2007-12-04 06:51:35 UTC (rev
7069)
@@ -17,7 +17,8 @@
input read,
input write,
output full,
- output empty);
+ output empty,
+ output [15:0] fifo_space);
wire [WIDTH-1:0] data_int;
wire empty_int, full_int, transfer;
@@ -30,7 +31,8 @@
longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
(.clk(clk),.rst(rst),
.datain(data_int), .write(transfer), .full(full_int),
- .dataout(dataout), .read(read), .empty(empty) );
+ .dataout(dataout), .read(read), .empty(empty),
+ .fifo_space(fifo_space) );
assign transfer = ~empty_int & ~full_int;
Modified: usrp2/trunk/fpga/control_lib/cascadefifo2.v
===================================================================
--- usrp2/trunk/fpga/control_lib/cascadefifo2.v 2007-12-04 06:50:40 UTC (rev
7068)
+++ usrp2/trunk/fpga/control_lib/cascadefifo2.v 2007-12-04 06:51:35 UTC (rev
7069)
@@ -14,7 +14,8 @@
input read,
input write,
output full,
- output empty);
+ output empty,
+ output [15:0] fifo_space);
wire [WIDTH-1:0] data_int, data_int2;
wire empty_int, full_int, transfer;
@@ -28,7 +29,8 @@
longfifo #(.WIDTH(WIDTH),.SIZE(SIZE)) longfifo
(.clk(clk),.rst(rst),
.datain(data_int), .write(transfer), .full(full_int),
- .dataout(data_int2), .read(transfer2), .empty(empty_int2) );
+ .dataout(data_int2), .read(transfer2), .empty(empty_int2),
+ .fifo_space(fifo_space) );
shortfifo #(.WIDTH(WIDTH)) shortfifo2
(.clk(clk),.rst(rst),
Modified: usrp2/trunk/fpga/control_lib/longfifo.v
===================================================================
--- usrp2/trunk/fpga/control_lib/longfifo.v 2007-12-04 06:50:40 UTC (rev
7068)
+++ usrp2/trunk/fpga/control_lib/longfifo.v 2007-12-04 06:51:35 UTC (rev
7069)
@@ -13,7 +13,8 @@
input read,
input write,
output full,
- output empty);
+ output empty,
+ output [15:0] fifo_space);
// Read side states
localparam EMPTY = 0;
@@ -26,7 +27,8 @@
wire [SIZE-1:0] fullness = wr_addr - rd_addr; // Approximate, for
simulation only
wire [SIZE-1:0] free_space = rd_addr - wr_addr - 2; // Approximate, for
SERDES flow control
reg empty_reg, full_reg;
-
+ assign fifo_space = {{16-SIZE{1'b0}},free_space};
+
always @(posedge clk)
if(rst)
wr_addr <= 0;
[Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] r7069 - usrp2/trunk/fpga/control_lib,
matt <=