[Commit-gnuradio] r7068 - usrp2/trunk/fpga/serdes

[matt]

Author: matt
Date: 2007-12-03 23:50:40 -0700 (Mon, 03 Dec 2007)
New Revision: 7068

Modified:
   usrp2/trunk/fpga/serdes/serdes.v
   usrp2/trunk/fpga/serdes/serdes_rx.v
   usrp2/trunk/fpga/serdes/serdes_tx.v
Log:
basic connections for flow control, disabled for now


Modified: usrp2/trunk/fpga/serdes/serdes.v
===================================================================
--- usrp2/trunk/fpga/serdes/serdes.v    2007-12-04 06:18:59 UTC (rev 7067)
+++ usrp2/trunk/fpga/serdes/serdes.v    2007-12-04 06:50:40 UTC (rev 7068)
@@ -14,17 +14,29 @@
      output [31:0] wr_dat_o, output wr_write_o, output wr_done_o, output 
wr_error_o,
      input wr_ready_i, input wr_full_i );
 
+   wire [15:0] fifo_space;
+   wire        xon_rcvd, xoff_rcvd, inhibit_tx, send_xon, send_xoff, sent;
    
    serdes_tx #(.FIFOSIZE(TXFIFOSIZE)) serdes_tx
      (.clk(clk),.rst(rst),
       
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
       
.rd_dat_i(rd_dat_i),.rd_read_o(rd_read_o),.rd_done_o(rd_done_o),.rd_error_o(rd_error_o),
-      .rd_sop_i(rd_sop_i),.rd_eop_i(rd_eop_i) );
+      .rd_sop_i(rd_sop_i),.rd_eop_i(rd_eop_i),
+      .inhibit_tx(inhibit_tx), .send_xon(send_xon), .send_xoff(send_xoff), 
.sent(sent) );
    
    serdes_rx #(.FIFOSIZE(RXFIFOSIZE)) serdes_rx
      (.clk(clk),.rst(rst),
       
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
       
.wr_dat_o(wr_dat_o),.wr_write_o(wr_write_o),.wr_done_o(wr_done_o),.wr_error_o(wr_error_o),
-      .wr_ready_i(wr_ready_i),.wr_full_i(wr_full_i) );
+      .wr_ready_i(wr_ready_i),.wr_full_i(wr_full_i),
+      .fifo_space(fifo_space), .xon_rcvd(xon_rcvd), .xoff_rcvd(xoff_rcvd) );
+
+   serdes_fc_tx serdes_fc_tx
+     (.clk(clk),.rst(rst),
+      .xon_rcvd(xon_rcvd),.xoff_rcvd(xoff_rcvd),.inhibit_tx(inhibit_tx) );
+
+   serdes_fc_rx #(.LWMARK(32),.HWMARK(128)) serdes_fc_rx
+     (.clk(clk),.rst(rst),
+      
.fifo_space(fifo_space),.send_xon(send_xon),.send_xoff(send_xoff),.sent(sent) );
    
 endmodule // serdes

Modified: usrp2/trunk/fpga/serdes/serdes_rx.v
===================================================================
--- usrp2/trunk/fpga/serdes/serdes_rx.v 2007-12-04 06:18:59 UTC (rev 7067)
+++ usrp2/trunk/fpga/serdes/serdes_rx.v 2007-12-04 06:50:40 UTC (rev 7068)
@@ -36,9 +36,13 @@
      output wr_done_o,
      output wr_error_o,
      input wr_ready_i,
-     input wr_full_i
+     input wr_full_i,
+
+     output [15:0] fifo_space,
+     output xon_rcvd, output xoff_rcvd
      );
-   
+
+   assign   xon_rcvd = 0; assign xoff_rcvd = 0;
    localparam K_COMMA = 8'b101_11100;     // 0xBC K28.5
    localparam K_IDLE = 8'b001_11100;      // 0x3C K28.1
    localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6
@@ -93,13 +97,7 @@
    
    assign      chosen_data = odd ? odd_data : even_data;
 
-/*   
    always @(posedge clk)
-     if(phase == 1)
-       line_i = {chosen_data[15:0], halfline};
- */
-
-   always @(posedge clk)
      if(rst) sop_i <= 0;
      else if(state == FIRSTLINE1) sop_i <= 1;
      else if(write_d) sop_i <= 0;
@@ -238,7 +236,8 @@
    cascadefifo2 #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo
      (.clk(clk),.rst(rst),
       .datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full),
-      .dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty) );
+      .dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty),
+      .fifo_space(fifo_space) );
    
    // Internal FIFO to Buffer interface
    reg                xfer_active;

Modified: usrp2/trunk/fpga/serdes/serdes_tx.v
===================================================================
--- usrp2/trunk/fpga/serdes/serdes_tx.v 2007-12-04 06:18:59 UTC (rev 7067)
+++ usrp2/trunk/fpga/serdes/serdes_tx.v 2007-12-04 06:50:40 UTC (rev 7068)
@@ -37,9 +37,16 @@
      output rd_done_o,
      output rd_error_o,
      input rd_sop_i,
-     input rd_eop_i
+     input rd_eop_i,
+
+     // Flow control interface
+     input inhibit_tx,
+     input send_xon,
+     input send_xoff,
+     output sent
      );
-   
+
+   assign   sent = 0;
    localparam K_COMMA = 8'b101_11100;     // 0xBC K28.5
    localparam K_IDLE = 8'b001_11100;      // 0x3C K28.1
    localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6
@@ -93,8 +100,6 @@
    reg [15:0]  second_word;
    reg [33:0]  pipeline;
    
-   wire        throttle_me = 0;   // Flow control here
-   
    assign      read = (state==RUN2) | ((state==IDLE) & ~empty & ~sop_o);  
    // 2nd half of above probably not necessary.  Just in case we get junk 
between packets
    
@@ -108,7 +113,7 @@
        case(state)
         IDLE :
           begin
-             if(sop_o & ~empty & ~throttle_me)
+             if(sop_o & ~empty & ~inhibit_tx)
                begin
                   {ser_tkmsb,ser_tklsb,ser_t} <= 
{2'b11,K_PKT_START,K_PKT_START};
                   state <= RUN1;
@@ -118,7 +123,7 @@
           end
         RUN1 :
           begin
-             if(empty | throttle_me)
+             if(empty | inhibit_tx)
                {ser_tkmsb,ser_tklsb,ser_t} <= {2'b11,K_COMMA,K_COMMA};
              else
                begin
@@ -158,7 +163,7 @@
        CRC <= 16'hFFFF;
      else if(state == IDLE)
        CRC <= 16'hFFFF;
-     else if( (~empty & ~throttle_me & (state==RUN1)) || (state==RUN2) )
+     else if( (~empty & ~inhibit_tx & (state==RUN1)) || (state==RUN2) )
        CRC <= nextCRC;
    
    CRC16_D16 crc_blk( (state==RUN1) ? data_o[15:0] : data_o[31:16], CRC, 
nextCRC);