[Commit-gnuradio] r7029 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2007-11-26 16:19:45 -0700 (Mon, 26 Nov 2007)
New Revision: 7029

Modified:
   usrp2/trunk/fpga/control_lib/longfifo.v
Log:
free space in fifo computation, plus remove some dead code


Modified: usrp2/trunk/fpga/control_lib/longfifo.v
===================================================================
--- usrp2/trunk/fpga/control_lib/longfifo.v     2007-11-26 23:17:18 UTC (rev 
7028)
+++ usrp2/trunk/fpga/control_lib/longfifo.v     2007-11-26 23:19:45 UTC (rev 
7029)
@@ -23,8 +23,8 @@
    reg [SIZE-1:0] wr_addr, rd_addr;
    reg [1:0]     read_state;
 
-   wire [SIZE-1:0] fullness = wr_addr - rd_addr;  // For simulation only
-
+   wire [SIZE-1:0] fullness = wr_addr - rd_addr;  // Approximate, for 
simulation only
+   wire [SIZE-1:0] free_space = rd_addr - wr_addr - 2;  // Approximate, for 
SERDES flow control
    reg           empty_reg, full_reg;
    
    always @(posedge clk)
@@ -93,15 +93,6 @@
      else if(write & ~read & (wr_addr == (rd_addr-3)))
        full_reg <= 1;
 
-/*   always @(posedge clk)
-     if(rst)
-       empty_reg <= 1;
-     else if(write & ~read)
-       empty_reg <= 0;
-     else if(read & ~write & (wr_addr == (rd_addr+1)))
-       empty_reg <= 1;
-  */
-   
    //assign empty = (read_state != READING);
    assign empty = empty_reg;