[avr-chat] Re: AVR-chat Digest, Vol 20, Issue 8

[Steve Franks]

Message: 4
Date: Thu, 21 Sep 2006 23:52:48 +0200 (MET DST)
From: address@hidden (Joerg Wunsch)
Subject: Re: [avr-chat] SPI interrupt slow?
To: address@hidden
Message-ID: < address@hidden>
Content-Type: text/plain; charset=iso-8859-1

"Steve Franks" <address@hidden> wrote:

> Anyone have thoughts on why I can set an output pin, jam data into
> the SPDR, and clear the output pin on interrupt on a Mega644 (on the
> 8MHz internal clock (SPI at clk/2)), and it takes 7uS, but if I do
> the same with a wait loop instead of the interrupt, it takes 3.5uS?

Interrupt startup takes a documented 5 cycles until the interrupt
vector will be jumped to (unless the interrupted instruction is a
multi-cycle one, when it will take even longer), plus another 3 cycles
for the typical JMP instruction that is placed on the interrupt vector
address.  That's already adding up to a microsecond in your case.

I guess the remainder of your 3.5 µs is due to the ISR prologue, in
particular register PUSHes will take their time (as they access RAM
which will always cost at least two cycles).

> In the real world, this means an AVR can only transfer about 100kB/s
> over the SPI interrupted, ...

Interrupt-driven SPI is really only useful for slow peers.

--
cheers, J"org               .-.-.   --... ...--   -.. .  DL8DTL

http://www.sax.de/~joerg/                         NIC: JW11-RIPE
Never trust an operating system you don't have sources for. ;-)





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End of AVR-chat Digest, Vol 20, Issue 8
***************************************

Thanks, as always Joerg.  I suspected as much.

Steve

-- 
Steve Franks, KE7BTE
Staff Engineer
La Palma Devices, LLC
http://www.lapalmadevices.com
(520) 312-0089