Re: [unclassified] Re: [avr-chat] BLDC control with ATmega128?

[Rick Mann]

On Feb 6, 2006, at 12:22 AM, David Brown wrote:

> No, it's not that simple.  With BLDC patterns, at any given time  
> only three
> FETs are active - either two on the top and one on the bottom, or vice
> versa, and you never have a pair with both the top and bottom side  
> doing
> work at the same time.  With PMSM patterns, every FET is active  
> within each
> 20 KHz (for example) PWM cycle.  The idle state, driving no power and
> ignoring dead time (BLDC patterns can ignore dead time, which is  
> nice), is
> with a 50% signal on all FETs (with the top and bottom sides out of  
> phase,
> obviously).  You could get away with 3 PWMs if you have the necessary
> external logic and FET drivers with built-in dead time generation, I
> suppose.

Hmm. I'm about to send a board off to get fabbed, and i want to make  
sure I didn't F- it all up...

Here's what I was thinking I could do (for hall-sensored BLDC): I  
have 3 PWMs (say, from Timer 1 on the '128) going to three
IR2104 MGDs, and 3 GPIOs going to the 2104's /SD pins (I guess those  
are basically extraneous). With the IR2104, a high input results in  
the high-side driver being on and the low-side driver being off. The  
reverse is true for a low input. Thus, a 50% duty cycle results in  
equal time on and off (out of phase), and with the LC circuit formed  
by the motor should result in 0 net current (this is the case for a  
brushed DC motor).

My thought was to increase the duty cycle on the two high-side half- 
bridge and decrease it on the low-side half-bridge (or vice versa if  
a stage that's the other way around). Won't that give me what I want?  
I realize you say above that that's how PMSMs are driven, but it  
seems like it would work for BLDC, too.

At this point, I've sort of committed the other three PWM outputs to  
other uses (pin change interrupts), and so it would be hard to change  
the design. I can make the GPIOs function that way if I generate  
interrupts on the other three PWMs and then write code to change the  
GPIO outputs to simulate PWM, but I'd hate to do this if I can avoid it.

(BTW, the reason it seems to me that you can get away with a single  
PWM, 3 GPIOs (to identify which side is on in each half-bridge) and  
external logic is because all the gates are driven with the same PWM  
waveform, right?)

What're your thoughts?

Thanks for all your help!

--
Rick