Am 22. Februar 2023 23:00:02 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>: On Wed, 22 Feb 2023, Bernhard Beschow wrote: Am 22. Februar 2023 21:12:01 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu
On Wed, 1 Mar 2023, Bernhard Beschow wrote: Am 1. März 2023 00:17:11 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>: MorphOS sets the ISA PIC to level sensitive mode but QEMU does not support that
Yes. 0x3c isn't supposed to be interpretet by hardware, and in general hardware can't: 0x3c is standardized for every PCI function which includes standalone PCI devices in particular. Standalone PCI
On Wed, 22 Feb 2023, Bernhard Beschow wrote: Am 22. Februar 2023 21:12:01 UTC schrieb BALATON Zoltan <balaton@eik.bme.hu>: On Wed, 22 Feb 2023, Bernhard Beschow wrote: Am 22. Februar 2023 19:25:16 UT
On Wed, 22 Feb 2023, Bernhard Beschow wrote: On Wed, Feb 22, 2023 at 4:38 PM Bernhard Beschow <shentey@gmail.com> wrote: On Tue, Feb 21, 2023 at 7:44 PM BALATON Zoltan <balaton@eik.bme.hu> wrote: Thi
On Wed, Feb 22, 2023 at 4:38 PM Bernhard Beschow <shentey@gmail.com> wrote: On Tue, Feb 21, 2023 at 7:44 PM BALATON Zoltan <balaton@eik.bme.hu> wrote: This series fixes PCI interrupts on the ppc/pega
Ping Patch is reviewed. Who will queue it? Daniel? Queued in gitlab.com/danielhb/qemu/tree/ppc-next. Thanks, Daniel Best regards, Bernhard -- Testing done: * `qemu-system-ppc -machine pegasos2 \ -rtc
mv64361_pcihost_map_irq() is a reimplementation of pci_swizzle_map_irq_fn(). Resolve this redundancy. Signed-off-by: Bernhard Beschow <shentey@gmail.com> -- Testing done: * `qemu-system-ppc -machine
Hi Daniel, Bernhard, On 27/10/22 11:47, Daniel Henrique Barboza wrote: On 10/27/22 05:21, Bernhard Beschow wrote: Am 16. September 2022 14:36:05 UTC schrieb "Philippe Mathieu-Daudé" <f4bug@amsat.org
On 10/27/22 05:21, Bernhard Beschow wrote: Am 16. September 2022 14:36:05 UTC schrieb "Philippe Mathieu-Daudé" <f4bug@amsat.org>: On 12/9/22 21:50, Bernhard Beschow wrote: Am 1. September 2022 11:41
v2: * Keep the call to pci_ide_create_devs() in board code for consistency (Zoltan) * Create rtc-time alias in board rather than in south bridge code * Remove stale comments about PCI functions v1: T
This series instantiates all PCI functions of the VT82xx southbridges in the southbridges themselves. For the IDE function this is especially important since its interrupt routing is configured in th
The functional changes are (the VOF ones need retesting with Pegasos2): (VOF) setprop will start failing if the machine class callback did not handle it; (VOF) unit addresses are lowered in path_offs
The functional changes are (the VOF ones need retesting with Pegasos2): (VOF) setprop will start failing if the machine class callback did not handle it; (VOF) unit addresses are lowered in path_offs
On Tue, 15 Jun 2021, Alexey Kardashevskiy wrote: On 6/7/21 01:46, BALATON Zoltan wrote: The pegasos2 board comes with an Open Firmware compliant ROM based on SmartFirmware but it has some changes tha
On 6/7/21 13:05, David Gibson wrote: On Fri, Jun 04, 2021 at 03:50:28PM +0200, BALATON Zoltan wrote: On Fri, 4 Jun 2021, David Gibson wrote: On Sun, May 30, 2021 at 07:33:01PM +0200, BALATON Zoltan w
Ok, but probably cleaned up to more modern qemu approaches. Yeah, fair enough. Ok, history lesson time. For a long time PAPR has been the document that described the OS environment for IBM POWER base
On Fri, 4 Jun 2021, David Gibson wrote: On Wed, Jun 02, 2021 at 02:29:29PM +0200, BALATON Zoltan wrote: On Wed, 2 Jun 2021, David Gibson wrote: On Thu, May 27, 2021 at 02:42:39PM +0200, BALATON Zolta
Sounds like a problem for someone else another time, then. No, I mean on the qemu side adding an optional hook which will intercept sc 0 instructions with the MOL magic register values and redirect t
This is kind of a subtle incompatibility between the traditional OF world and the flat tree world. In traditional OF, the unit address (bit after the @) doesn't exist as a string. Instead when you do
On Wed, 2 Jun 2021, David Gibson wrote: On Thu, May 27, 2021 at 02:42:39PM +0200, BALATON Zoltan wrote: On Thu, 27 May 2021, David Gibson wrote: On Tue, May 25, 2021 at 12:08:45PM +0200, BALATON Zolt
Oh, it definitely won't work with KVM HV. Uh... I guess so? Maybe. I never know much about MOL to begin with, and anything I did know was a decade or more ago so I've probably forgotten. Note that if
Hello, Two more problems I've found while testing with pegasos2 but I'm not sure how to fix them: On Thu, 20 May 2021, Alexey Kardashevskiy wrote: diff --git a/hw/ppc/vof.c b/hw/ppc/vof.c new file mo
On Thu, 27 May 2021, David Gibson wrote: On Tue, May 25, 2021 at 12:08:45PM +0200, BALATON Zoltan wrote: On Tue, 25 May 2021, David Gibson wrote: On Mon, May 24, 2021 at 12:55:07PM +0200, BALATON Zol
Eh, since you'll need to modify KVM anyway, it probably makes just as much sense to modify it to catch the 'sc 1' as MoL's magic thingy. rtas_ld() and rtas_st() should only be used for reading/writin
Uh, I guess modify it with the if-hv-available thing. Don't move it under the ifdef, it still makes logical sense for 32-bit systems, even though the HV available side should never trip. -- David Gib
On Tue, 25 May 2021, David Gibson wrote: On Mon, May 24, 2021 at 12:55:07PM +0200, BALATON Zoltan wrote: On Mon, 24 May 2021, David Gibson wrote: On Sun, May 23, 2021 at 07:09:26PM +0200, BALATON Zol
On Tue, 25 May 2021, David Gibson wrote: On Mon, May 24, 2021 at 02:42:30PM +0200, BALATON Zoltan wrote: On Mon, 24 May 2021, David Gibson wrote: On Sun, May 23, 2021 at 07:09:26PM +0200, BALATON Zol
Uh.. maybe. I think ISA bridges at least sometimes behave differently from regular PCI devices or bridges, because legacy. Also note that it's probably IO space you need to map in, not MMIO space. --
It should be caught elsehwere. Specifically, when the SDR1 SPR is registered, on CPUs with a hypervisor mode it should be registered as hypervisor privileged, so the general mtspr dispatch logic shou
The vhyp shouldn't affect normal system calls, 'sc 1' is specifically for hypercalls, as opposed to normal 'sc' (a.k.a. 'sc 0'), and the vhyp only intercepts the hypercall version (after all Linux on
On 24/05/2021 20:55, BALATON Zoltan wrote: On Mon, 24 May 2021, David Gibson wrote: On Sun, May 23, 2021 at 07:09:26PM +0200, BALATON Zoltan wrote: On Sun, 23 May 2021, BALATON Zoltan wrote: On Sun,
On Mon, 24 May 2021, David Gibson wrote: On Sun, May 23, 2021 at 07:09:26PM +0200, BALATON Zoltan wrote: On Sun, 23 May 2021, BALATON Zoltan wrote: On Sun, 23 May 2021, Alexey Kardashevskiy wrote: On
On Mon, 24 May 2021, David Gibson wrote: On Sun, May 23, 2021 at 07:09:26PM +0200, BALATON Zoltan wrote: On Sun, 23 May 2021, BALATON Zoltan wrote: On Sun, 23 May 2021, Alexey Kardashevskiy wrote: On
Yes, definitely sounds like you'll need an RTAS implementation. Ah.. right. So, vhyp was designed for the PAPR use case, where we want to model the CPU when it's in supervisor and user mode, but not
On Sun, 23 May 2021, BALATON Zoltan wrote: On Sun, 23 May 2021, Alexey Kardashevskiy wrote: One thing to note about PCI is that normally I think the client expects the firmware to do PCI probing and
On Sun, 23 May 2021, Alexey Kardashevskiy wrote: On 23/05/2021 02:46, BALATON Zoltan wrote: On Sat, 22 May 2021, BALATON Zoltan wrote: On Sat, 22 May 2021, BALATON Zoltan wrote: On Sat, 22 May 2021,
On 23/05/2021 02:46, BALATON Zoltan wrote: On Sat, 22 May 2021, BALATON Zoltan wrote: On Sat, 22 May 2021, BALATON Zoltan wrote: On Sat, 22 May 2021, Alexey Kardashevskiy wrote: VOF itself does not p
On Sat, 22 May 2021, BALATON Zoltan wrote: On Sat, 22 May 2021, BALATON Zoltan wrote: On Sat, 22 May 2021, Alexey Kardashevskiy wrote: VOF itself does not prints anything in this patch. However it se
On Mon, 17 May 2021, BALATON Zoltan wrote: On Mon, 17 May 2021, Alexey Kardashevskiy wrote: On 5/17/21 09:34, BALATON Zoltan wrote: On Sat, 15 May 2021, BALATON Zoltan wrote: On Sat, 15 May 2021, BAL
On Mon, 17 May 2021, Alexey Kardashevskiy wrote: On 5/17/21 09:34, BALATON Zoltan wrote: On Sat, 15 May 2021, BALATON Zoltan wrote: On Sat, 15 May 2021, BALATON Zoltan wrote: On Thu, 22 Apr 2021, Ale
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based on the Marvell MV64361 system controller and the VIA VT8231 integrated south bridge/superio chips. It can
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based on the Marvell MV64361 system controller and the VIA VT8231 integrated south bridge/superio chips. It can
Well, you could always lobby the distro to include it. Honestly I think the distros would probably choose not to include something for such a niche case, even if it was enabled by default upstream. A
On Wed, 24 Mar 2021, David Gibson wrote: On Tue, Mar 23, 2021 at 02:01:27PM +0100, BALATON Zoltan wrote: On Tue, 23 Mar 2021, David Gibson wrote: On Wed, Mar 17, 2021 at 02:17:51AM +0100, BALATON Zol
Not convinced, sorry. If it's not usable out of the box, having to build from source is kind of expected. Or you could convince someone (or do it yourself) to provide prebuild binaries for this purpo
On Tue, 23 Mar 2021, Mark Cave-Ayland wrote: On 23/03/2021 12:54, BALATON Zoltan wrote: On Wed, 10 Mar 2021, BALATON Zoltan wrote: In VIA super south bridge the io ranges of superio components (paral
On Wed, 10 Mar 2021, BALATON Zoltan wrote: In VIA super south bridge the io ranges of superio components (parallel and serial ports and FDC) can be controlled by superio config registers to set thei
On Tue, 23 Mar 2021, David Gibson wrote: On Wed, Mar 17, 2021 at 02:17:51AM +0100, BALATON Zoltan wrote: Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based o
Oh, sorry about the comment in the previous patch. I don't think we can have this default to enabled while it requires a non-free ROM to start. -- David Gibson | I'll have my music baroque, and my co
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based on the Marvell MV64361 system controller and the VIA VT8231 integrated south bridge/superio chips. It can
On Tue, 16 Mar 2021, BALATON Zoltan wrote: On Tue, 16 Mar 2021, Mark Cave-Ayland wrote: On 16/03/2021 17:25, BALATON Zoltan wrote: On Tue, 16 Mar 2021, Mark Cave-Ayland wrote: On 16/03/2021 13:06, BA
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based on the Marvell MV64361 system controller and the VIA VT8231 integrated south bridge/superio chips. It can
On Tue, 16 Mar 2021, Mark Cave-Ayland wrote: On 16/03/2021 17:25, BALATON Zoltan wrote: On Tue, 16 Mar 2021, Mark Cave-Ayland wrote: On 16/03/2021 13:06, BALATON Zoltan wrote: The PATCH 1 doesn't see
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based on the Marvell MV64361 system controller and the VIA VT8231 integrated south bridge/superio chips. It can
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based on the Marvell MV64361 system controller and the VIA VT8231 integrated south bridge/superio chips. It can
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based on the Marvell MV64361 system controller and the VIA VT8231 integrated south bridge/superio chips. It can
On Thu, 4 Mar 2021, BALATON Zoltan wrote: On Wed, 3 Mar 2021, David Gibson wrote: On Tue, Mar 02, 2021 at 10:13:19AM +0100, BALATON Zoltan wrote: On Tue, 2 Mar 2021, Philippe Mathieu-Daudé wrote: On
On Wed, 3 Mar 2021, David Gibson wrote: On Tue, Mar 02, 2021 at 10:13:19AM +0100, BALATON Zoltan wrote: On Tue, 2 Mar 2021, Philippe Mathieu-Daudé wrote: On 2/25/21 8:47 PM, BALATON Zoltan wrote: Ad
Including me as reviewer is fine for now. Fwiw, Red Hat's internal guidelines have the opinion that the years don't matter that much and are usually out of date, so they suggest simply "Copyright Red
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based on the Marvell MV64361 system controller and the VIA VT8231 integrated south bridge/superio chips. It can
To clarify the confusion with this simple smiley, I meant I'm glad you found someone interested in being reviewer with your board, it was not a mockery... You might get ride of this one by rebasing/i
On Tue, 2 Mar 2021, Philippe Mathieu-Daudé wrote: On 2/25/21 8:47 PM, BALATON Zoltan wrote: Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based on the Marvel
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based on the Marvell MV64361 system controller and the VIA VT8231 integrated south bridge/superio chips. It can
I'd suggest pegasos2_cpu_reset() for clarity. With the current name I'd assume it was the machine reset function. -- David Gibson | I'll have my music baroque, and my code david AT gibson.dropbear.id
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based on the Marvell MV64361 system controller and the VIA VT8231 integrated south bridge/superio chips. It can
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based on the Marvell MV64361 system controller and the VIA VT8231 integrated south bridge/superio chips. It can
Add new machine called pegasos2 emulating the Genesi/bPlan Pegasos II, a PowerPC board based on the Marvell MV64361 system controller and the VIA VT8231 integrated south bridge/superio chips. It can
This adds DDC support to ati-vga and connects i2c-ddc to it. This allows at least MacOS with an ATI ndrv, Linux radeonfb and MorphOS to get monitor EDID info (although MorphOS splash screen is not di
On 1/27/19 7:19 AM, Mark Cave-Ayland wrote: Could this make the loop slower? I certainly haven't noticed any obvious performance difference during testing (OS X uses merge quite a bit for display re
Hi Zoltan, here more info about the issues 1. System time is going slower than expected in AROS (can be seen e.g. in Time Prefs). The seconds advance but much slower than they should. (AROS boot iso
Hi Zoltan, i had been ask in the amigaos scene plus i ask to Max Tretene (Acube uboot dev) some help about the sam infos that you need. for now they send me this datasheet links hope it can help your
Then pass a pointer to them to the C handler code? If you don't fix up the reason why the interrupt occured in the first place it will simply happen again. Alex
On Mon, 28 Jul 2014, Alexander Graf wrote: On 27.06.14 23:34, BALATON Zoltan wrote: On Thu, 26 Jun 2014, Alexander Graf wrote: On 26.06.14 13:20, BALATON Zoltan wrote: On Thu, 26 Jun 2014, Alexander
Great to see progress with the Mac99 emulation. I got less time for it lately but can someone please answer this question? On Fri, 27 Jun 2014, BALATON Zoltan wrote: On Thu, 26 Jun 2014, Alexander Gr
On 27.06.14 23:34, BALATON Zoltan wrote: On Thu, 26 Jun 2014, Alexander Graf wrote: On 26.06.14 13:20, BALATON Zoltan wrote: On Thu, 26 Jun 2014, Alexander Graf wrote: You could enable write protecti
Hello, Great to see progress with the Mac99 emulation. I got less time for it lately but can someone please answer this question? On Fri, 27 Jun 2014, BALATON Zoltan wrote: On Thu, 26 Jun 2014, Alexa
On Thu, 26 Jun 2014, Alexander Graf wrote: On 26.06.14 13:20, BALATON Zoltan wrote: On Thu, 26 Jun 2014, Alexander Graf wrote: You could enable write protection on the first page before you enter the
Am 24.06.2014 um 00:41 hat Mark Cave-Ayland geschrieben: Not to my knowledge. Block devices allowing byte-granularity accesses (or can you even call them block devices any more then?) seem to be some
I forgot that one. I've now rerun with DEBUG_IDE_ATAPI enabled. Here is with the patch failing: DBDMA: writel 0x0000000000000d0c <= 0x00e599f0 DBDMA: channel 0x1a reg 0x3 DBDMA: dbdma_cmdptr_load 0x0
Unfortunately it seems MorphOS cannot boot with this patch. It hangs while trying to read the TOC from the CD. Debug output with DEBUG_MACIO and DEBUG_DBDMA enabled shows: DBDMA: writel 0x00000000000
I am looking at the test case source code and do not see how you are setting the reserved bit. Maybe I am missing some cleverness in how the test is built? include <prom.h> void stwxtest(void) { unsi
The results show that the stwx instruction with reserved bit set does not change status bits and does not generate an exception on any CPU tested (G3 and G4) so it is most probably just ignored as we
at hw/ide/macio.c:55 at hw/ide/macio.c:225 14777932, req_count=804, is_last=1) at hw/misc/macio/mac_dbdma.c:334 at hw/misc/macio/mac_dbdma.c:489 at hw/misc/macio/mac_dbdma.c:531 at hw/misc/macio/mac_
MorphOS and Darwin are definitely doing things differently. I hope someone who understands what is happening can explain it why one of them works while the other doesn't. Which I hope is what I'm tr
That patch would be 80fc95d8bdaf3392106b131a97ca701fd374489a in QEMU master. I've tried reverting it and Darwin still boots (without -M mac99) up to the point where it asks to install as before but
On Apr 11, 2014, at 8:28 AM, address@hidden wrote: On 20.03.14 11:16, BALATON Zoltan wrote: On Sat, 15 Mar 2014, BALATON Zoltan wrote: Try to better match the memory map of a PowerMac3,1 model by mov
On 20.03.14 11:16, BALATON Zoltan wrote: On Sat, 15 Mar 2014, BALATON Zoltan wrote: Try to better match the memory map of a PowerMac3,1 model by moving the pci-cfg mappings to where they are on a rea
On Sat, 15 Mar 2014, BALATON Zoltan wrote: Try to better match the memory map of a PowerMac3,1 model by moving the pci-cfg mappings to where they are on a real machine. Also add the VGA card after th