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From: | Palmer Dabbelt |
Subject: | Re: [PATCH trivial for 7.2] hw/ssi/sifive_spi.c: spelling: reigster |
Date: | Tue, 08 Nov 2022 14:11:02 -0800 (PST) |
On Sat, 05 Nov 2022 04:53:29 PDT (-0700), mjt@tls.msk.ru wrote:
Fixes: 0694dabe9763847f3010b54ab3ec7d367d2f0ff0
Not sure if I missed something in QEMU land, but those are usually listed more like
Fixes: 0694dabe97 ("hw/ssi: Add SiFive SPI controller support") Checkpatch isn't failing, though. Either way Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Thanks!
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru> --- hw/ssi/sifive_spi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c index 03540cf5ca..1b4a401ca1 100644 --- a/hw/ssi/sifive_spi.c +++ b/hw/ssi/sifive_spi.c @@ -267,7 +267,7 @@ static void sifive_spi_write(void *opaque, hwaddr addr, case R_RXDATA: case R_IP: qemu_log_mask(LOG_GUEST_ERROR, - "%s: invalid write to read-only reigster 0x%" + "%s: invalid write to read-only register 0x%" HWADDR_PRIx " with 0x%x\n", __func__, addr << 2, value); break;
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