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[PATCH v3 18/57] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld,
From: |
Richard Henderson |
Subject: |
[PATCH v3 18/57] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st} |
Date: |
Mon, 24 Apr 2023 06:40:26 +0100 |
Interpret the variable argument placement in the caller. Shift some
code around slightly to share more between softmmu and user-only.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/loongarch64/tcg-target.c.inc | 100 +++++++++++++------------------
1 file changed, 42 insertions(+), 58 deletions(-)
diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc
index 0940788c6f..2e3c67054b 100644
--- a/tcg/loongarch64/tcg-target.c.inc
+++ b/tcg/loongarch64/tcg-target.c.inc
@@ -1049,39 +1049,31 @@ static void tcg_out_qemu_ld_indexed(TCGContext *s,
TCGReg rd, TCGReg rj,
}
}
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, TCGType type)
+static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
+ MemOpIdx oi, TCGType data_type)
{
- TCGReg addr_regl;
- TCGReg data_regl;
- MemOpIdx oi;
- MemOp opc;
-#if defined(CONFIG_SOFTMMU)
+ MemOp opc = get_memop(oi);
+ TCGReg base, index;
+
+#ifdef CONFIG_SOFTMMU
tcg_insn_unit *label_ptr[1];
-#else
- unsigned a_bits;
-#endif
- TCGReg base;
- data_regl = *args++;
- addr_regl = *args++;
- oi = *args++;
- opc = get_memop(oi);
-
-#if defined(CONFIG_SOFTMMU)
- tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 1);
- base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
- tcg_out_qemu_ld_indexed(s, data_regl, base, TCG_REG_TMP2, opc, type);
- add_qemu_ldst_label(s, 1, oi, type,
- data_regl, addr_regl,
- s->code_ptr, label_ptr);
+ tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 1);
+ index = TCG_REG_TMP2;
#else
- a_bits = get_alignment_bits(opc);
+ unsigned a_bits = get_alignment_bits(opc);
if (a_bits) {
- tcg_out_test_alignment(s, true, addr_regl, a_bits);
+ tcg_out_test_alignment(s, true, addr_reg, a_bits);
}
- base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
- TCGReg guest_base_reg = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
- tcg_out_qemu_ld_indexed(s, data_regl, base, guest_base_reg, opc, type);
+ index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
+#endif
+
+ base = tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0);
+ tcg_out_qemu_ld_indexed(s, data_reg, base, index, opc, data_type);
+
+#ifdef CONFIG_SOFTMMU
+ add_qemu_ldst_label(s, true, oi, data_type, data_reg, addr_reg,
+ s->code_ptr, label_ptr);
#endif
}
@@ -1109,39 +1101,31 @@ static void tcg_out_qemu_st_indexed(TCGContext *s,
TCGReg data,
}
}
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, TCGType type)
+static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
+ MemOpIdx oi, TCGType data_type)
{
- TCGReg addr_regl;
- TCGReg data_regl;
- MemOpIdx oi;
- MemOp opc;
-#if defined(CONFIG_SOFTMMU)
+ MemOp opc = get_memop(oi);
+ TCGReg base, index;
+
+#ifdef CONFIG_SOFTMMU
tcg_insn_unit *label_ptr[1];
-#else
- unsigned a_bits;
-#endif
- TCGReg base;
- data_regl = *args++;
- addr_regl = *args++;
- oi = *args++;
- opc = get_memop(oi);
-
-#if defined(CONFIG_SOFTMMU)
- tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0);
- base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
- tcg_out_qemu_st_indexed(s, data_regl, base, TCG_REG_TMP2, opc);
- add_qemu_ldst_label(s, 0, oi, type,
- data_regl, addr_regl,
- s->code_ptr, label_ptr);
+ tcg_out_tlb_load(s, addr_reg, oi, label_ptr, 0);
+ index = TCG_REG_TMP2;
#else
- a_bits = get_alignment_bits(opc);
+ unsigned a_bits = get_alignment_bits(opc);
if (a_bits) {
- tcg_out_test_alignment(s, false, addr_regl, a_bits);
+ tcg_out_test_alignment(s, false, addr_reg, a_bits);
}
- base = tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0);
- TCGReg guest_base_reg = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
- tcg_out_qemu_st_indexed(s, data_regl, base, guest_base_reg, opc);
+ index = USE_GUEST_BASE ? TCG_GUEST_BASE_REG : TCG_REG_ZERO;
+#endif
+
+ base = tcg_out_zext_addr_if_32_bit(s, addr_reg, TCG_REG_TMP0);
+ tcg_out_qemu_st_indexed(s, data_reg, base, index, opc);
+
+#ifdef CONFIG_SOFTMMU
+ add_qemu_ldst_label(s, false, oi, data_type, data_reg, addr_reg,
+ s->code_ptr, label_ptr);
#endif
}
@@ -1564,16 +1548,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
break;
case INDEX_op_qemu_ld_i32:
- tcg_out_qemu_ld(s, args, TCG_TYPE_I32);
+ tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, args, TCG_TYPE_I64);
+ tcg_out_qemu_ld(s, a0, a1, a2, TCG_TYPE_I64);
break;
case INDEX_op_qemu_st_i32:
- tcg_out_qemu_st(s, args, TCG_TYPE_I32);
+ tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I32);
break;
case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, args, TCG_TYPE_I64);
+ tcg_out_qemu_st(s, a0, a1, a2, TCG_TYPE_I64);
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
--
2.34.1
- Re: [PATCH v3 06/57] tcg/i386: Generalize multi-part load overlap test, (continued)
- [PATCH v3 07/57] tcg/i386: Introduce HostAddress, Richard Henderson, 2023/04/24
- [PATCH v3 09/57] tcg/i386: Introduce tcg_out_testi, Richard Henderson, 2023/04/24
- [PATCH v3 10/57] tcg/i386: Introduce prepare_host_addr, Richard Henderson, 2023/04/24
- [PATCH v3 08/57] tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load, Richard Henderson, 2023/04/24
- [PATCH v3 12/57] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st}, Richard Henderson, 2023/04/24
- [PATCH v3 11/57] tcg/i386: Use indexed addressing for softmmu fast path, Richard Henderson, 2023/04/24
- [PATCH v3 14/57] tcg/aarch64: Introduce prepare_host_addr, Richard Henderson, 2023/04/24
- [PATCH v3 18/57] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st},
Richard Henderson <=
- [PATCH v3 13/57] tcg/aarch64: Introduce HostAddress, Richard Henderson, 2023/04/24
- [PATCH v3 16/57] tcg/arm: Introduce HostAddress, Richard Henderson, 2023/04/24
- [PATCH v3 37/57] tcg: Widen helper_*_st[bw]_mmu val arguments, Richard Henderson, 2023/04/24
- [PATCH v3 15/57] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/04/24
- [PATCH v3 17/57] tcg/arm: Introduce prepare_host_addr, Richard Henderson, 2023/04/24
- [PATCH v3 19/57] tcg/loongarch64: Introduce HostAddress, Richard Henderson, 2023/04/24
- [PATCH v3 21/57] tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/04/24