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[PATCH 39/42] tcg/s390x: Use ALGFR in constructing host address for qemu
From: |
Richard Henderson |
Subject: |
[PATCH 39/42] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st |
Date: |
Fri, 7 Apr 2023 19:43:11 -0700 |
Rather than zero-extend the guest address into a register,
use an add instruction which zero-extends the second input.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
tcg/s390x/tcg-target.c.inc | 38 ++++++++++++++++++++++----------------
1 file changed, 22 insertions(+), 16 deletions(-)
diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc
index 7d6cb30a06..b53eb70f24 100644
--- a/tcg/s390x/tcg-target.c.inc
+++ b/tcg/s390x/tcg-target.c.inc
@@ -149,6 +149,7 @@ typedef enum S390Opcode {
RRE_ALGR = 0xb90a,
RRE_ALCR = 0xb998,
RRE_ALCGR = 0xb988,
+ RRE_ALGFR = 0xb91a,
RRE_CGR = 0xb920,
RRE_CLGR = 0xb921,
RRE_DLGR = 0xb987,
@@ -1716,8 +1717,10 @@ static void tcg_out_qemu_st_direct(TCGContext *s, MemOp
opc, TCGReg data,
QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0);
QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19));
-/* Load and compare a TLB entry, leaving the flags set. Loads the TLB
- addend into R2. Returns a register with the santitized guest address. */
+/*
+ * Load and compare a TLB entry, leaving the flags set.
+ * Loads the TLB addend and returns the register.
+ */
static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg addr_reg, MemOp opc,
int mem_index, bool is_ld)
{
@@ -1761,12 +1764,7 @@ static TCGReg tcg_out_tlb_read(TCGContext *s, TCGReg
addr_reg, MemOp opc,
tcg_out_insn(s, RXY, LG, TCG_REG_R2, TCG_REG_R2, TCG_REG_NONE,
offsetof(CPUTLBEntry, addend));
-
- if (TARGET_LONG_BITS == 32) {
- tcg_out_ext32u(s, TCG_REG_R3, addr_reg);
- return TCG_REG_R3;
- }
- return addr_reg;
+ return TCG_REG_R2;
}
static void add_qemu_ldst_label(TCGContext *s, bool is_ld, MemOpIdx oi,
@@ -1888,16 +1886,20 @@ static void tcg_out_qemu_ld(TCGContext* s, TCGReg
data_reg, TCGReg addr_reg,
#ifdef CONFIG_SOFTMMU
unsigned mem_index = get_mmuidx(oi);
tcg_insn_unit *label_ptr;
- TCGReg base_reg;
+ TCGReg addend;
- base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1);
+ addend = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 1);
tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
label_ptr = s->code_ptr;
s->code_ptr += 1;
- tcg_out_qemu_ld_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
-
+ if (TARGET_LONG_BITS == 32) {
+ tcg_out_insn(s, RRE, ALGFR, addend, addr_reg);
+ tcg_out_qemu_ld_direct(s, opc, data_reg, addend, TCG_REG_NONE, 0);
+ } else {
+ tcg_out_qemu_ld_direct(s, opc, data_reg, addend, addr_reg, 0);
+ }
add_qemu_ldst_label(s, 1, oi, d_type, data_reg, addr_reg,
s->code_ptr, label_ptr);
#else
@@ -1920,16 +1922,20 @@ static void tcg_out_qemu_st(TCGContext* s, TCGReg
data_reg, TCGReg addr_reg,
#ifdef CONFIG_SOFTMMU
unsigned mem_index = get_mmuidx(oi);
tcg_insn_unit *label_ptr;
- TCGReg base_reg;
+ TCGReg addend;
- base_reg = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0);
+ addend = tcg_out_tlb_read(s, addr_reg, opc, mem_index, 0);
tcg_out16(s, RI_BRC | (S390_CC_NE << 4));
label_ptr = s->code_ptr;
s->code_ptr += 1;
- tcg_out_qemu_st_direct(s, opc, data_reg, base_reg, TCG_REG_R2, 0);
-
+ if (TARGET_LONG_BITS == 32) {
+ tcg_out_insn(s, RRE, ALGFR, addend, addr_reg);
+ tcg_out_qemu_st_direct(s, opc, data_reg, addend, TCG_REG_NONE, 0);
+ } else {
+ tcg_out_qemu_st_direct(s, opc, data_reg, addend, addr_reg, 0);
+ }
add_qemu_ldst_label(s, 0, oi, d_type, data_reg, addr_reg,
s->code_ptr, label_ptr);
#else
--
2.34.1
- [PATCH 29/42] tcg: Move TCGLabelQemuLdst to tcg.c, (continued)
- [PATCH 29/42] tcg: Move TCGLabelQemuLdst to tcg.c, Richard Henderson, 2023/04/07
- [PATCH 30/42] tcg: Introduce tcg_out_ld_helper_args, Richard Henderson, 2023/04/07
- [PATCH 32/42] tcg/loongarch64: Simplify constraints on qemu_ld/st, Richard Henderson, 2023/04/07
- [PATCH 33/42] tcg/mips: Reorg tcg_out_tlb_load, Richard Henderson, 2023/04/07
- [PATCH 31/42] tcg: Introduce tcg_out_st_helper_args, Richard Henderson, 2023/04/07
- [PATCH 35/42] tcg/ppc: Reorg tcg_out_tlb_read, Richard Henderson, 2023/04/07
- [PATCH 38/42] tcg/riscv: Simplify constraints on qemu_ld/st, Richard Henderson, 2023/04/07
- [PATCH 37/42] tcg/ppc: Remove unused constraints A, B, C, D, Richard Henderson, 2023/04/07
- [PATCH 36/42] tcg/ppc: Adjust constraints on qemu_ld/st, Richard Henderson, 2023/04/07
- [PATCH 34/42] tcg/mips: Simplify constraints on qemu_ld/st, Richard Henderson, 2023/04/07
- [PATCH 39/42] tcg/s390x: Use ALGFR in constructing host address for qemu_ld/st,
Richard Henderson <=
- [PATCH 40/42] tcg/s390x: Simplify constraints on qemu_ld/st, Richard Henderson, 2023/04/07
- [PATCH 41/42] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return, Richard Henderson, 2023/04/07
- [PATCH 42/42] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st}, Richard Henderson, 2023/04/07