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[PATCH v2 34/76] target/m68k: Drop free_cond
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From: |
Richard Henderson |
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Subject: |
[PATCH v2 34/76] target/m68k: Drop free_cond |
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Date: |
Sun, 26 Feb 2023 19:24:23 -1000 |
Translators are no longer required to free tcg temporaries.
Remove the g1 and g2 members of DisasCompare, as they were
used to track which temps needed to be freed.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/m68k/translate.c | 40 ----------------------------------------
1 file changed, 40 deletions(-)
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index b3cd3e87e1..d7237b6a99 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -1249,8 +1249,6 @@ static int gen_ea_fp(CPUM68KState *env, DisasContext *s,
uint16_t insn,
typedef struct {
TCGCond tcond;
- bool g1;
- bool g2;
TCGv v1;
TCGv v2;
} DisasCompare;
@@ -1263,7 +1261,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s,
int cond)
/* The CC_OP_CMP form can handle most normal comparisons directly. */
if (op == CC_OP_CMPB || op == CC_OP_CMPW || op == CC_OP_CMPL) {
- c->g1 = c->g2 = 1;
c->v1 = QREG_CC_N;
c->v2 = QREG_CC_V;
switch (cond) {
@@ -1281,7 +1278,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s,
int cond)
goto done;
case 10: /* PL */
case 11: /* MI */
- c->g1 = c->g2 = 0;
c->v2 = tcg_const_i32(0);
c->v1 = tmp = tcg_temp_new();
tcg_gen_sub_i32(tmp, QREG_CC_N, QREG_CC_V);
@@ -1298,8 +1294,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s,
int cond)
}
}
- c->g1 = 1;
- c->g2 = 0;
c->v2 = tcg_const_i32(0);
switch (cond) {
@@ -1383,7 +1377,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext *s,
int cond)
case 2: /* HI (!C && !Z) -> !(C || Z)*/
case 3: /* LS (C || Z) */
c->v1 = tmp = tcg_temp_new();
- c->g1 = 0;
tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
tcg_gen_or_i32(tmp, tmp, QREG_CC_C);
tcond = TCG_COND_NE;
@@ -1411,14 +1404,12 @@ static void gen_cc_cond(DisasCompare *c, DisasContext
*s, int cond)
case 12: /* GE (!(N ^ V)) */
case 13: /* LT (N ^ V) */
c->v1 = tmp = tcg_temp_new();
- c->g1 = 0;
tcg_gen_xor_i32(tmp, QREG_CC_N, QREG_CC_V);
tcond = TCG_COND_LT;
break;
case 14: /* GT (!(Z || (N ^ V))) */
case 15: /* LE (Z || (N ^ V)) */
c->v1 = tmp = tcg_temp_new();
- c->g1 = 0;
tcg_gen_setcond_i32(TCG_COND_EQ, tmp, QREG_CC_Z, c->v2);
tcg_gen_neg_i32(tmp, tmp);
tmp2 = tcg_temp_new();
@@ -1436,16 +1427,6 @@ static void gen_cc_cond(DisasCompare *c, DisasContext
*s, int cond)
c->tcond = tcond;
}
-static void free_cond(DisasCompare *c)
-{
- if (!c->g1) {
- tcg_temp_free(c->v1);
- }
- if (!c->g2) {
- tcg_temp_free(c->v2);
- }
-}
-
static void gen_jmpcc(DisasContext *s, int cond, TCGLabel *l1)
{
DisasCompare c;
@@ -1453,7 +1434,6 @@ static void gen_jmpcc(DisasContext *s, int cond, TCGLabel
*l1)
gen_cc_cond(&c, s, cond);
update_cc_op(s);
tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
- free_cond(&c);
}
/* Force a TB lookup after an instruction that changes the CPU state. */
@@ -1512,7 +1492,6 @@ DISAS_INSN(scc)
tmp = tcg_temp_new();
tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
- free_cond(&c);
tcg_gen_neg_i32(tmp, tmp);
DEST_EA(env, insn, OS_BYTE, tmp, NULL);
@@ -4887,7 +4866,6 @@ static void do_trapcc(DisasContext *s, DisasCompare *c)
s->base.is_jmp = DISAS_NEXT;
}
}
- free_cond(c);
}
DISAS_INSN(trapcc)
@@ -5383,9 +5361,7 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext
*s, int cond)
{
TCGv fpsr;
- c->g1 = 1;
c->v2 = tcg_const_i32(0);
- c->g2 = 0;
/* TODO: Raise BSUN exception. */
fpsr = tcg_temp_new();
gen_load_fcr(s, fpsr, M68K_FPSR);
@@ -5398,14 +5374,12 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext
*s, int cond)
case 1: /* EQual Z */
case 17: /* Signaling EQual Z */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
c->tcond = TCG_COND_NE;
break;
case 2: /* Ordered Greater Than !(A || Z || N) */
case 18: /* Greater Than !(A || Z || N) */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_andi_i32(c->v1, fpsr,
FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
c->tcond = TCG_COND_EQ;
@@ -5413,7 +5387,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext
*s, int cond)
case 3: /* Ordered Greater than or Equal Z || !(A || N) */
case 19: /* Greater than or Equal Z || !(A || N) */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_Z | FPSR_CC_N);
@@ -5424,7 +5397,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext
*s, int cond)
case 4: /* Ordered Less Than !(!N || A || Z); */
case 20: /* Less Than !(!N || A || Z); */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_xori_i32(c->v1, fpsr, FPSR_CC_N);
tcg_gen_andi_i32(c->v1, c->v1, FPSR_CC_N | FPSR_CC_A | FPSR_CC_Z);
c->tcond = TCG_COND_EQ;
@@ -5432,7 +5404,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext
*s, int cond)
case 5: /* Ordered Less than or Equal Z || (N && !A) */
case 21: /* Less than or Equal Z || (N && !A) */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_A));
tcg_gen_andc_i32(c->v1, fpsr, c->v1);
@@ -5442,35 +5413,30 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext
*s, int cond)
case 6: /* Ordered Greater or Less than !(A || Z) */
case 22: /* Greater or Less than !(A || Z) */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
c->tcond = TCG_COND_EQ;
break;
case 7: /* Ordered !A */
case 23: /* Greater, Less or Equal !A */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
c->tcond = TCG_COND_EQ;
break;
case 8: /* Unordered A */
case 24: /* Not Greater, Less or Equal A */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A);
c->tcond = TCG_COND_NE;
break;
case 9: /* Unordered or Equal A || Z */
case 25: /* Not Greater or Less then A || Z */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z);
c->tcond = TCG_COND_NE;
break;
case 10: /* Unordered or Greater Than A || !(N || Z)) */
case 26: /* Not Less or Equal A || !(N || Z)) */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
tcg_gen_andi_i32(fpsr, fpsr, FPSR_CC_A | FPSR_CC_N);
@@ -5481,7 +5447,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext
*s, int cond)
case 11: /* Unordered or Greater or Equal A || Z || !N */
case 27: /* Not Less Than A || Z || !N */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
tcg_gen_xori_i32(c->v1, c->v1, FPSR_CC_N);
c->tcond = TCG_COND_NE;
@@ -5489,7 +5454,6 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext
*s, int cond)
case 12: /* Unordered or Less Than A || (N && !Z) */
case 28: /* Not Greater than or Equal A || (N && !Z) */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
tcg_gen_shli_i32(c->v1, c->v1, ctz32(FPSR_CC_N) - ctz32(FPSR_CC_Z));
tcg_gen_andc_i32(c->v1, fpsr, c->v1);
@@ -5499,14 +5463,12 @@ static void gen_fcc_cond(DisasCompare *c, DisasContext
*s, int cond)
case 13: /* Unordered or Less or Equal A || Z || N */
case 29: /* Not Greater Than A || Z || N */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_A | FPSR_CC_Z | FPSR_CC_N);
c->tcond = TCG_COND_NE;
break;
case 14: /* Not Equal !Z */
case 30: /* Signaling Not Equal !Z */
c->v1 = tcg_temp_new();
- c->g1 = 0;
tcg_gen_andi_i32(c->v1, fpsr, FPSR_CC_Z);
c->tcond = TCG_COND_EQ;
break;
@@ -5526,7 +5488,6 @@ static void gen_fjmpcc(DisasContext *s, int cond,
TCGLabel *l1)
gen_fcc_cond(&c, s, cond);
update_cc_op(s);
tcg_gen_brcond_i32(c.tcond, c.v1, c.v2, l1);
- free_cond(&c);
}
DISAS_INSN(fbcc)
@@ -5562,7 +5523,6 @@ DISAS_INSN(fscc)
tmp = tcg_temp_new();
tcg_gen_setcond_i32(c.tcond, tmp, c.v1, c.v2);
- free_cond(&c);
tcg_gen_neg_i32(tmp, tmp);
DEST_EA(env, insn, OS_BYTE, tmp, NULL);
--
2.34.1
- [PATCH v2 26/76] target/hexagon: Drop tcg_temp_free from gen_tcg_funcs.py, (continued)
- [PATCH v2 26/76] target/hexagon: Drop tcg_temp_free from gen_tcg_funcs.py, Richard Henderson, 2023/02/27
- [PATCH v2 27/76] target/hexagon/idef-parser: Drop tcg_temp_free, Richard Henderson, 2023/02/27
- [PATCH v2 28/76] target/hexagon/idef-parser: Drop HexValue.is_manual, Richard Henderson, 2023/02/27
- [PATCH v2 29/76] target/hppa: Drop tcg_temp_free, Richard Henderson, 2023/02/27
- [PATCH v2 31/76] target/loongarch: Drop temp_new, Richard Henderson, 2023/02/27
- [PATCH v2 30/76] target/i386: Drop tcg_temp_free, Richard Henderson, 2023/02/27
- [PATCH v2 32/76] target/loongarch: Drop tcg_temp_free, Richard Henderson, 2023/02/27
- [PATCH v2 34/76] target/m68k: Drop free_cond,
Richard Henderson <=
- [PATCH v2 35/76] target/m68k: Drop tcg_temp_free, Richard Henderson, 2023/02/27
- [PATCH v2 33/76] target/m68k: Drop mark_to_release, Richard Henderson, 2023/02/27
- [PATCH v2 38/76] target/mips: Drop tcg_temp_free from mips16e_translate.c.inc, Richard Henderson, 2023/02/27
- [PATCH v2 39/76] target/mips: Drop tcg_temp_free from msa_translate.c, Richard Henderson, 2023/02/27
- [PATCH v2 36/76] target/microblaze: Drop tcg_temp_free, Richard Henderson, 2023/02/27
- [PATCH v2 37/76] target/mips: Drop tcg_temp_free from micromips_translate.c.inc, Richard Henderson, 2023/02/27
- [PATCH v2 41/76] target/mips: Drop tcg_temp_free from nanomips_translate.c.inc, Richard Henderson, 2023/02/27
- [PATCH v2 40/76] target/mips: Drop tcg_temp_free from mxu_translate.c, Richard Henderson, 2023/02/27
- [PATCH v2 42/76] target/mips: Drop tcg_temp_free from octeon_translate.c, Richard Henderson, 2023/02/27
- [PATCH v2 44/76] target/mips: Drop tcg_temp_free from tx79_translate.c, Richard Henderson, 2023/02/27