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[PATCH v2 03/15] RISC-V: Adding XTheadBa ISA extension
From: |
Christoph Muellner |
Subject: |
[PATCH v2 03/15] RISC-V: Adding XTheadBa ISA extension |
Date: |
Fri, 23 Dec 2022 19:00:03 +0100 |
From: Christoph Müllner <christoph.muellner@vrull.eu>
This patch adds support for the XTheadBa ISA extension.
The patch uses the T-Head specific decoder and translation.
Changes in v2:
- Add ISA_EXT_DATA_ENTRY()
- Split XtheadB* extension into individual commits
- Use single decoder for XThead extensions
Co-developed-by: Philipp Tomsich <philipp.tomsich@vrull.eu>
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu.h | 1 +
target/riscv/insn_trans/trans_xthead.c.inc | 39 ++++++++++++++++++++++
target/riscv/translate.c | 3 +-
target/riscv/xthead.decode | 22 ++++++++++++
5 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a848836d2e..809b6eb4ed 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -108,6 +108,7 @@ static const struct isa_ext_data isa_edata_arr[] = {
ISA_EXT_DATA_ENTRY(svinval, true, PRIV_VERSION_1_12_0, ext_svinval),
ISA_EXT_DATA_ENTRY(svnapot, true, PRIV_VERSION_1_12_0, ext_svnapot),
ISA_EXT_DATA_ENTRY(svpbmt, true, PRIV_VERSION_1_12_0, ext_svpbmt),
+ ISA_EXT_DATA_ENTRY(xtheadba, true, PRIV_VERSION_1_11_0, ext_xtheadba),
ISA_EXT_DATA_ENTRY(xtheadcmo, true, PRIV_VERSION_1_11_0, ext_xtheadcmo),
ISA_EXT_DATA_ENTRY(xtheadsync, true, PRIV_VERSION_1_11_0, ext_xtheadsync),
ISA_EXT_DATA_ENTRY(xventanacondops, true, PRIV_VERSION_1_12_0,
ext_XVentanaCondOps),
@@ -1062,6 +1063,7 @@ static Property riscv_cpu_extensions[] = {
DEFINE_PROP_BOOL("zmmul", RISCVCPU, cfg.ext_zmmul, false),
/* Vendor-specific custom extensions */
+ DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
DEFINE_PROP_BOOL("xtheadcmo", RISCVCPU, cfg.ext_xtheadcmo, false),
DEFINE_PROP_BOOL("xtheadsync", RISCVCPU, cfg.ext_xtheadsync, false),
DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,
false),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 4d3da2acfa..ec2588a0f0 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -465,6 +465,7 @@ struct RISCVCPUConfig {
uint64_t mimpid;
/* Vendor-specific custom extensions */
+ bool ext_xtheadba;
bool ext_xtheadcmo;
bool ext_xtheadsync;
bool ext_XVentanaCondOps;
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc
b/target/riscv/insn_trans/trans_xthead.c.inc
index 6009d61c81..79e1f5bde9 100644
--- a/target/riscv/insn_trans/trans_xthead.c.inc
+++ b/target/riscv/insn_trans/trans_xthead.c.inc
@@ -16,6 +16,12 @@
* this program. If not, see <http://www.gnu.org/licenses/>.
*/
+#define REQUIRE_XTHEADBA(ctx) do { \
+ if (!ctx->cfg_ptr->ext_xtheadba) { \
+ return false; \
+ } \
+} while (0)
+
#define REQUIRE_XTHEADCMO(ctx) do { \
if (!ctx->cfg_ptr->ext_xtheadcmo) { \
return false; \
@@ -28,6 +34,39 @@
} \
} while (0)
+/* XTheadBa */
+
+/*
+ * th.addsl is similar to sh[123]add (from Zba), but not an
+ * alternative encoding: while sh[123] applies the shift to rs1,
+ * th.addsl shifts rs2.
+ */
+
+#define GEN_TH_ADDSL(SHAMT) \
+static void gen_th_addsl##SHAMT(TCGv ret, TCGv arg1, TCGv arg2) \
+{ \
+ TCGv t = tcg_temp_new(); \
+ tcg_gen_shli_tl(t, arg2, SHAMT); \
+ tcg_gen_add_tl(ret, t, arg1); \
+ tcg_temp_free(t); \
+}
+
+GEN_TH_ADDSL(1)
+GEN_TH_ADDSL(2)
+GEN_TH_ADDSL(3)
+
+#define GEN_TRANS_TH_ADDSL(SHAMT) \
+static bool trans_th_addsl##SHAMT(DisasContext *ctx, \
+ arg_th_addsl##SHAMT * a) \
+{ \
+ REQUIRE_XTHEADBA(ctx); \
+ return gen_arith(ctx, a, EXT_NONE, gen_th_addsl##SHAMT, NULL); \
+}
+
+GEN_TRANS_TH_ADDSL(1)
+GEN_TRANS_TH_ADDSL(2)
+GEN_TRANS_TH_ADDSL(3)
+
/* XTheadCmo */
static inline int priv_level(DisasContext *ctx)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index c40617662a..7b35f1d71b 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -127,7 +127,8 @@ static bool always_true_p(DisasContext *ctx
__attribute__((__unused__)))
static bool has_xthead_p(DisasContext *ctx __attribute__((__unused__)))
{
- return ctx->cfg_ptr->ext_xtheadcmo || ctx->cfg_ptr->ext_xtheadsync;
+ return ctx->cfg_ptr->ext_xtheadba || ctx->cfg_ptr->ext_xtheadcmo ||
+ ctx->cfg_ptr->ext_xtheadsync;
}
#define MATERIALISE_EXT_PREDICATE(ext) \
diff --git a/target/riscv/xthead.decode b/target/riscv/xthead.decode
index 1d86f3a012..b149f13018 100644
--- a/target/riscv/xthead.decode
+++ b/target/riscv/xthead.decode
@@ -2,6 +2,7 @@
# Translation routines for the instructions of the XThead* ISA extensions
#
# Copyright (c) 2022 Christoph Muellner, christoph.muellner@vrull.eu
+# Dr. Philipp Tomsich, philipp.tomsich@vrull.eu
#
# SPDX-License-Identifier: LGPL-2.1-or-later
#
@@ -9,12 +10,33 @@
# https://github.com/T-head-Semi/thead-extension-spec/releases/latest
# Fields:
+%rd 7:5
%rs1 15:5
%rs2 20:5
+# Argument sets
+&r rd rs1 rs2 !extern
+
# Formats
@sfence_vm ....... ..... ..... ... ..... ....... %rs1
@rs2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
+@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
+
+# XTheadBa
+# Instead of defining a new encoding, we simply use the decoder to
+# extract the imm[0:1] field and dispatch to separate translation
+# functions (mirroring the `sh[123]add` instructions from Zba and
+# the regular RVI `add` instruction.
+#
+# The only difference between sh[123]add and addsl is that the shift
+# is applied to rs1 (for addsl) instead of rs2 (for sh[123]add).
+#
+# Note that shift-by-0 is a valid operation according to the manual.
+# This will be equivalent to a regular add.
+add 0000000 ..... ..... 001 ..... 0001011 @r
+th_addsl1 0000001 ..... ..... 001 ..... 0001011 @r
+th_addsl2 0000010 ..... ..... 001 ..... 0001011 @r
+th_addsl3 0000011 ..... ..... 001 ..... 0001011 @r
# XTheadCmo
th_dcache_call 0000000 00001 00000 000 00000 0001011
--
2.38.1
- [PATCH v2 00/15] Add support for the T-Head vendor extensions, Christoph Muellner, 2022/12/23
- [PATCH v2 02/15] RISC-V: Adding XTheadSync ISA extension, Christoph Muellner, 2022/12/23
- [PATCH v2 05/15] RISC-V: Adding XTheadBs ISA extension, Christoph Muellner, 2022/12/23
- [PATCH v2 06/15] RISC-V: Adding XTheadCondMov ISA extension, Christoph Muellner, 2022/12/23
- [PATCH v2 01/15] RISC-V: Adding XTheadCmo ISA extension, Christoph Muellner, 2022/12/23
- [PATCH v2 03/15] RISC-V: Adding XTheadBa ISA extension,
Christoph Muellner <=
- [PATCH v2 04/15] RISC-V: Adding XTheadBb ISA extension, Christoph Muellner, 2022/12/23
- [PATCH v2 09/15] RISC-V: Adding T-Head MemIdx extension, Christoph Muellner, 2022/12/23
- [PATCH v2 07/15] RISC-V: Adding T-Head multiply-accumulate instructions, Christoph Muellner, 2022/12/23
- [PATCH v2 11/15] RISC-V: Adding T-Head XMAE support, Christoph Muellner, 2022/12/23
- [PATCH v2 15/15] target/riscv: add a MAINTAINERS entry for XThead* extension support, Christoph Muellner, 2022/12/23
- [PATCH v2 08/15] RISC-V: Adding T-Head MemPair extension, Christoph Muellner, 2022/12/23
- [PATCH v2 10/15] RISC-V: Adding T-Head FMemIdx extension, Christoph Muellner, 2022/12/23
- [PATCH v2 12/15] RISC-V: Set minimum priv version for Zfh to 1.11, Christoph Muellner, 2022/12/23
- [PATCH v2 14/15] RISC-V: Adding XTheadFmv ISA extension, Christoph Muellner, 2022/12/23
- [PATCH v2 13/15] RISC-V: Add initial support for T-Head C906, Christoph Muellner, 2022/12/23