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[PATCH 08/10] target/riscv/cpu: Restrict sysemu-specific fields from CPU
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH 08/10] target/riscv/cpu: Restrict sysemu-specific fields from CPUArchState |
Date: |
Fri, 16 Dec 2022 23:05:37 +0100 |
The 'hwaddr' type is only available / meaningful on system emulation.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
target/riscv/cpu.h | 34 ++++++++++++++++++----------------
1 file changed, 18 insertions(+), 16 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index fc1f72e5c3..bd4e16d946 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -368,16 +368,6 @@ struct CPUArchState {
uint64_t menvcfg;
target_ulong senvcfg;
uint64_t henvcfg;
-#endif
- target_ulong cur_pmmask;
- target_ulong cur_pmbase;
-
- float_status fp_status;
-
- /* Fields from here on are preserved across CPU reset. */
- QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
- QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
- bool vstime_irq;
hwaddr kernel_addr;
hwaddr fdt_addr;
@@ -388,6 +378,16 @@ struct CPUArchState {
uint64_t kvm_timer_compare;
uint64_t kvm_timer_state;
uint64_t kvm_timer_frequency;
+#endif
+ target_ulong cur_pmmask;
+ target_ulong cur_pmbase;
+
+ float_status fp_status;
+
+ /* Fields from here on are preserved across CPU reset. */
+ QEMUTimer *stimer; /* Internal timer for S-mode interrupt */
+ QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */
+ bool vstime_irq;
};
OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU)
@@ -553,12 +553,20 @@ bool riscv_cpu_virt_enabled(CPURISCVState *env);
void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
bool riscv_cpu_two_stage_lookup(int mmu_idx);
int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
+#ifndef CONFIG_USER_ONLY
+hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
G_NORETURN void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
MMUAccessType access_type, int
mmu_idx,
uintptr_t retaddr);
bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
MMUAccessType access_type, int mmu_idx,
bool probe, uintptr_t retaddr);
+void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
+ vaddr addr, unsigned size,
+ MMUAccessType access_type,
+ int mmu_idx, MemTxAttrs attrs,
+ MemTxResult response, uintptr_t retaddr);
+#endif
char *riscv_isa_string(RISCVCPU *cpu);
void riscv_cpu_list(void);
@@ -566,12 +574,6 @@ void riscv_cpu_list(void);
#define cpu_mmu_index riscv_cpu_mmu_index
#ifndef CONFIG_USER_ONLY
-void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
- vaddr addr, unsigned size,
- MMUAccessType access_type,
- int mmu_idx, MemTxAttrs attrs,
- MemTxResult response, uintptr_t retaddr);
-hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts);
--
2.38.1
- Re: [PATCH 03/10] target/loongarch/cpu: Remove unused "sysbus.h" header, (continued)
- [PATCH 04/10] target/loongarch/cpu: Restrict "memory.h" header to sysemu, Philippe Mathieu-Daudé, 2022/12/16
- [PATCH 05/10] target/m68k/helper: Include missing "cpu.h" header, Philippe Mathieu-Daudé, 2022/12/16
- [PATCH 06/10] target/ppc/helper: Include missing "cpu.h" header, Philippe Mathieu-Daudé, 2022/12/16
- [PATCH 07/10] target/ppc/internal: Restrict MMU declarations to sysemu, Philippe Mathieu-Daudé, 2022/12/16
- [PATCH 08/10] target/riscv/cpu: Restrict sysemu-specific fields from CPUArchState,
Philippe Mathieu-Daudé <=
- [PATCH 09/10] target/sparc/sysemu: Remove pointless CONFIG_USER_ONLY guard, Philippe Mathieu-Daudé, 2022/12/16
- [PATCH 10/10] target/xtensa/cpu: Include missing "memory.h" header, Philippe Mathieu-Daudé, 2022/12/16