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[PATCH 2/5] target/riscv: Update VS timer whenever htimedelta changes
From: |
Anup Patel |
Subject: |
[PATCH 2/5] target/riscv: Update VS timer whenever htimedelta changes |
Date: |
Thu, 27 Oct 2022 22:17:40 +0530 |
The htimedelta[h] CSR has impact on the VS timer comparison so we
should call riscv_timer_write_timecmp() whenever htimedelta changes.
Fixes: 3ec0fe18a31f ("target/riscv: Add vstimecmp suppor")
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
target/riscv/csr.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 716f9d960e..4b1a608260 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -2722,6 +2722,8 @@ static RISCVException read_htimedelta(CPURISCVState *env,
int csrno,
static RISCVException write_htimedelta(CPURISCVState *env, int csrno,
target_ulong val)
{
+ RISCVCPU *cpu = env_archcpu(env);
+
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -2731,6 +2733,12 @@ static RISCVException write_htimedelta(CPURISCVState
*env, int csrno,
} else {
env->htimedelta = val;
}
+
+ if (cpu->cfg.ext_sstc && env->rdtime_fn) {
+ riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ env->htimedelta, MIP_VSTIP);
+ }
+
return RISCV_EXCP_NONE;
}
@@ -2748,11 +2756,19 @@ static RISCVException read_htimedeltah(CPURISCVState
*env, int csrno,
static RISCVException write_htimedeltah(CPURISCVState *env, int csrno,
target_ulong val)
{
+ RISCVCPU *cpu = env_archcpu(env);
+
if (!env->rdtime_fn) {
return RISCV_EXCP_ILLEGAL_INST;
}
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
+
+ if (cpu->cfg.ext_sstc && env->rdtime_fn) {
+ riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp,
+ env->htimedelta, MIP_VSTIP);
+ }
+
return RISCV_EXCP_NONE;
}
--
2.34.1