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Re: [PATCH v3 0/2] Enhance maximum priority support of PLIC
From: |
Alistair Francis |
Subject: |
Re: [PATCH v3 0/2] Enhance maximum priority support of PLIC |
Date: |
Wed, 12 Oct 2022 08:47:19 +1000 |
On Mon, Oct 3, 2022 at 2:18 PM Jim Shu <jim.shu@sifive.com> wrote:
>
> This patchset fixes hard-coded maximum priority of interrupt priority
> register and also changes this register to WARL field to align the PLIC
> spec.
>
> Changelog:
>
> v3:
> * fix opposite of power-of-2 max priority checking expression.
>
> v2:
> * change interrupt priority register to WARL field.
>
> Jim Shu (2):
> hw/intc: sifive_plic: fix hard-coded max priority level
> hw/intc: sifive_plic: change interrupt priority register to WARL field
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> hw/intc/sifive_plic.c | 25 ++++++++++++++++++++++---
> 1 file changed, 22 insertions(+), 3 deletions(-)
>
> --
> 2.17.1
>
>