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[PATCH v6 05/23] target/riscv: Allow setting CPU feature from machine/de
From: |
Anup Patel |
Subject: |
[PATCH v6 05/23] target/riscv: Allow setting CPU feature from machine/device emulation |
Date: |
Thu, 30 Dec 2021 18:05:21 +0530 |
From: Anup Patel <anup.patel@wdc.com>
The machine or device emulation should be able to force set certain
CPU features because:
1) We can have certain CPU features which are in-general optional
but implemented by RISC-V CPUs on the machine.
2) We can have devices which require a certain CPU feature. For example,
AIA IMSIC devices expect AIA CSRs implemented by RISC-V CPUs.
Signed-off-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.c | 11 +++--------
target/riscv/cpu.h | 5 +++++
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index f4dbc766c2..9f1a4d1088 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -124,11 +124,6 @@ static void set_vext_version(CPURISCVState *env, int
vext_ver)
env->vext_ver = vext_ver;
}
-static void set_feature(CPURISCVState *env, int feature)
-{
- env->features |= (1ULL << feature);
-}
-
static void set_resetvec(CPURISCVState *env, target_ulong resetvec)
{
#ifndef CONFIG_USER_ONLY
@@ -434,18 +429,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
if (cpu->cfg.mmu) {
- set_feature(env, RISCV_FEATURE_MMU);
+ riscv_set_feature(env, RISCV_FEATURE_MMU);
}
if (cpu->cfg.pmp) {
- set_feature(env, RISCV_FEATURE_PMP);
+ riscv_set_feature(env, RISCV_FEATURE_PMP);
/*
* Enhanced PMP should only be available
* on harts with PMP support
*/
if (cpu->cfg.epmp) {
- set_feature(env, RISCV_FEATURE_EPMP);
+ riscv_set_feature(env, RISCV_FEATURE_EPMP);
}
}
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 6895ac138c..1bdd03731f 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -344,6 +344,11 @@ static inline bool riscv_feature(CPURISCVState *env, int
feature)
return env->features & (1ULL << feature);
}
+static inline void riscv_set_feature(CPURISCVState *env, int feature)
+{
+ env->features |= (1ULL << feature);
+}
+
#include "cpu_user.h"
extern const char * const riscv_int_regnames[];
--
2.25.1
- [PATCH v6 00/23] QEMU RISC-V AIA support, Anup Patel, 2021/12/30
- [PATCH v6 01/23] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Anup Patel, 2021/12/30
- [PATCH v6 02/23] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel, 2021/12/30
- [PATCH v6 03/23] target/riscv: Implement hgeie and hgeip CSRs, Anup Patel, 2021/12/30
- [PATCH v6 04/23] target/riscv: Improve delivery of guest external interrupts, Anup Patel, 2021/12/30
- [PATCH v6 05/23] target/riscv: Allow setting CPU feature from machine/device emulation,
Anup Patel <=
- [PATCH v6 06/23] target/riscv: Add AIA cpu feature, Anup Patel, 2021/12/30
- [PATCH v6 07/23] target/riscv: Add defines for AIA CSRs, Anup Patel, 2021/12/30
- [PATCH v6 08/23] target/riscv: Allow AIA device emulation to set ireg rmw callback, Anup Patel, 2021/12/30
- [PATCH v6 09/23] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2021/12/30
- [PATCH v6 10/23] target/riscv: Implement AIA CSRs for 64 local interrupts on RV32, Anup Patel, 2021/12/30
- [PATCH v6 11/23] target/riscv: Implement AIA hvictl and hviprioX CSRs, Anup Patel, 2021/12/30
- [PATCH v6 12/23] target/riscv: Implement AIA interrupt filtering CSRs, Anup Patel, 2021/12/30
- [PATCH v6 13/23] target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs, Anup Patel, 2021/12/30
- [PATCH v6 14/23] target/riscv: Implement AIA xiselect and xireg CSRs, Anup Patel, 2021/12/30
- [PATCH v6 15/23] target/riscv: Implement AIA IMSIC interface CSRs, Anup Patel, 2021/12/30