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Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores
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From: |
Anup Patel |
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Subject: |
Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores |
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Date: |
Thu, 16 Dec 2021 11:28:12 +0530 |
On Thu, Dec 16, 2021 at 10:27 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Linux supports up to 32 cores for both 32-bit and 64-bit RISC-V, so
> let's set that as the maximum for the virt board.
>
> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/435
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Overall, no issues with this patch. I have added PATCH23 in
the AIA v5 series which allows upto 512 CPUs . This is a hard
limit based on address space based on PLIC, ACLINT, IMSIC,
and APLIC address utilization and is also suitable for both RV32
and RV64.
IMO, we should keep QEMU VIRT_CPUS_MAX as high as
possible to allow any kind of software Linux, OpenSBI, FreeBSD,
Xvisor, Xen, etc. Let the guest software decide it's own limit (such
as NR_CPUS of Linux).
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Regards,
Anup
> ---
> include/hw/riscv/virt.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
> index b8ef99f348..6e9f61ccd9 100644
> --- a/include/hw/riscv/virt.h
> +++ b/include/hw/riscv/virt.h
> @@ -24,7 +24,7 @@
> #include "hw/block/flash.h"
> #include "qom/object.h"
>
> -#define VIRT_CPUS_MAX 8
> +#define VIRT_CPUS_MAX 32
> #define VIRT_SOCKETS_MAX 8
>
> #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
> --
> 2.31.1
>
>
- Re: [PATCH v2 4/9] hw/intc: sifive_plic: Cleanup remaining functions, (continued)
- [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental, Alistair Francis, 2021/12/15
- [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default, Alistair Francis, 2021/12/15
- [PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation, Alistair Francis, 2021/12/15
- [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores, Alistair Francis, 2021/12/15
- Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores,
Anup Patel <=
- Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores, Bin Meng, 2021/12/20
- [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency, Alistair Francis, 2021/12/15