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Re: [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by defa
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From: |
Anup Patel |
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Subject: |
Re: [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default |
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Date: |
Thu, 16 Dec 2021 11:22:41 +0530 |
On Thu, Dec 16, 2021 at 10:29 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>
> Let's enable the Hypervisor extension by default. This doesn't affect
> named CPUs (such as lowrisc-ibex or sifive-u54) but does enable the
> Hypervisor extensions by default for the virt machine.
>
> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Looks good to me.
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Regards,
Anup
> ---
> target/riscv/cpu.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 1edb2771b4..013a8760b5 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -626,7 +626,7 @@ static Property riscv_cpu_properties[] = {
> DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true),
> DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true),
> DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true),
> - DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, false),
> + DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true),
> DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true),
> DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true),
> DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true),
> --
> 2.31.1
>
>
- Re: [PATCH v2 1/9] hw/intc: sifive_plic: Add a reset function, (continued)
- [PATCH v2 2/9] hw/intc: sifive_plic: Cleanup the write function, Alistair Francis, 2021/12/15
- [PATCH v2 3/9] hw/intc: sifive_plic: Cleanup the read function, Alistair Francis, 2021/12/15
- [PATCH v2 4/9] hw/intc: sifive_plic: Cleanup remaining functions, Alistair Francis, 2021/12/15
- [PATCH v2 5/9] target/riscv: Mark the Hypervisor extension as non experimental, Alistair Francis, 2021/12/15
- [PATCH v2 6/9] target/riscv: Enable the Hypervisor extension by default, Alistair Francis, 2021/12/15
- [PATCH v2 7/9] hw/riscv: Use error_fatal for SoC realisation, Alistair Francis, 2021/12/15
- [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores, Alistair Francis, 2021/12/15
- Re: [PATCH v2 8/9] hw/riscv: virt: Allow support for 32 cores, Bin Meng, 2021/12/20
- [PATCH v2 9/9] hw/riscv: virt: Set the clock-frequency, Alistair Francis, 2021/12/15