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[PATCH v7 08/18] target/riscv: moving some insns close to similar insns
From: |
Frédéric Pétrot |
Subject: |
[PATCH v7 08/18] target/riscv: moving some insns close to similar insns |
Date: |
Mon, 13 Dec 2021 17:38:24 +0100 |
lwu and ld are functionally close to the other loads, but were after the
stores in the source file.
Similarly, xor was away from or and and by two arithmetic functions, while
the immediate versions were nicely put together.
This patch moves the aforementioned loads after lhu, and xor above or,
where they more logically belong.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++++++++-------------
1 file changed, 17 insertions(+), 17 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index 51607b3d40..710f5e6a85 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -176,6 +176,18 @@ static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
return gen_load(ctx, a, MO_TEUW);
}
+static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
+{
+ REQUIRE_64BIT(ctx);
+ return gen_load(ctx, a, MO_TEUL);
+}
+
+static bool trans_ld(DisasContext *ctx, arg_ld *a)
+{
+ REQUIRE_64BIT(ctx);
+ return gen_load(ctx, a, MO_TEUQ);
+}
+
static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
{
TCGv addr = get_gpr(ctx, a->rs1, EXT_NONE);
@@ -207,18 +219,6 @@ static bool trans_sw(DisasContext *ctx, arg_sw *a)
return gen_store(ctx, a, MO_TESL);
}
-static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
-{
- REQUIRE_64BIT(ctx);
- return gen_load(ctx, a, MO_TEUL);
-}
-
-static bool trans_ld(DisasContext *ctx, arg_ld *a)
-{
- REQUIRE_64BIT(ctx);
- return gen_load(ctx, a, MO_TEUQ);
-}
-
static bool trans_sd(DisasContext *ctx, arg_sd *a)
{
REQUIRE_64BIT(ctx);
@@ -317,11 +317,6 @@ static bool trans_sltu(DisasContext *ctx, arg_sltu *a)
return gen_arith(ctx, a, EXT_SIGN, gen_sltu);
}
-static bool trans_xor(DisasContext *ctx, arg_xor *a)
-{
- return gen_logic(ctx, a, tcg_gen_xor_tl);
-}
-
static bool trans_srl(DisasContext *ctx, arg_srl *a)
{
return gen_shift(ctx, a, EXT_ZERO, tcg_gen_shr_tl);
@@ -332,6 +327,11 @@ static bool trans_sra(DisasContext *ctx, arg_sra *a)
return gen_shift(ctx, a, EXT_SIGN, tcg_gen_sar_tl);
}
+static bool trans_xor(DisasContext *ctx, arg_xor *a)
+{
+ return gen_logic(ctx, a, tcg_gen_xor_tl);
+}
+
static bool trans_or(DisasContext *ctx, arg_or *a)
{
return gen_logic(ctx, a, tcg_gen_or_tl);
--
2.34.1
- [PATCH v7 04/18] target/riscv: additional macros to check instruction support, (continued)
- [PATCH v7 04/18] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/12/13
- [PATCH v7 02/18] exec/memop: Adding signed quad and octo defines, Frédéric Pétrot, 2021/12/13
- [PATCH v7 03/18] qemu/int128: addition of div/rem 128-bit operations, Frédéric Pétrot, 2021/12/13
- [PATCH v7 05/18] target/riscv: separation of bitwise logic and arithmetic helpers, Frédéric Pétrot, 2021/12/13
- [PATCH v7 01/18] exec/memop: Adding signedness to quad definitions, Frédéric Pétrot, 2021/12/13
- [PATCH v7 06/18] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/12/13
- [PATCH v7 09/18] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/12/13
- [PATCH v7 17/18] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/12/13
- [PATCH v7 13/18] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/12/13
- [PATCH v7 15/18] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/12/13
- [PATCH v7 08/18] target/riscv: moving some insns close to similar insns,
Frédéric Pétrot <=
- [PATCH v7 12/18] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/12/13
- [PATCH v7 18/18] target/riscv: actual functions to realize crs 128-bit insns, Frédéric Pétrot, 2021/12/13
- [PATCH v7 10/18] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/12/13
- [PATCH v7 14/18] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/12/13
- [PATCH v7 11/18] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/12/13
- [PATCH v7 07/18] target/riscv: setup everything for rv64 to support rv128 execution, Frédéric Pétrot, 2021/12/13
- [PATCH v7 16/18] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/12/13