qemu-riscv
[Top][All Lists]
Advanced

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

Re: [PATCH 2/5] target/riscv: debug: Implement debug related TCGCPUOps


From: Richard Henderson
Subject: Re: [PATCH 2/5] target/riscv: debug: Implement debug related TCGCPUOps
Date: Fri, 29 Oct 2021 12:36:35 -0700
User-agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/29/21 8:25 AM, Bin Meng wrote:
+void riscv_cpu_debug_excp_handler(CPUState *cs)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs);
+    CPURISCVState *env = &cpu->env;
+
+    if (cs->watchpoint_hit) {
+        if (cs->watchpoint_hit->flags & BP_CPU) {
+            cs->watchpoint_hit = NULL;
+            riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, GETPC());
+        }
+    } else {
+        if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) {
+            riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, GETPC());
+        }
+    }
+}

GETPC is only to be used by handlers called from TCG generated code.
You want 0 to indicate that unwinding is not needed, as it has been done for you already by generic code.


r~



reply via email to

[Prev in Thread] Current Thread [Next in Thread]