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[PATCH v4 00/22] QEMU RISC-V AIA support
From: |
Anup Patel |
Subject: |
[PATCH v4 00/22] QEMU RISC-V AIA support |
Date: |
Tue, 26 Oct 2021 12:12:05 +0530 |
The advanced interrupt architecture (AIA) extends the per-HART local
interrupt support. Along with this, it also adds IMSIC (MSI contrllor)
and Advanced PLIC (wired interrupt controller).
The latest AIA draft specification can be found here:
https://github.com/riscv/riscv-aia/releases/download/0.2-draft.27/riscv-interrupts-027.pdf
This series adds RISC-V AIA support in QEMU which includes emulating all
AIA local CSRs, APLIC, and IMSIC. Only AIA local interrupt filtering is
not implemented because we don't have any local interrupt greater than 12.
To enable AIA in QEMU, use one of the following:
1) Only AIA local interrupt CSRs: Pass "x-aia=true" as CPU paramenter
in the QEMU command-line
2) Only APLIC for virt machine: Pass "aia=aplic" as machine parameter
in the QEMU command-line
3) Both APLIC and IMSIC for virt machine: Pass "aia=aplic-imsic" as
machine parameter in the QEMU command-line
4) Both APLIC and IMSIC with 2 guest files for virt machine: Pass
"aia=aplic-imsic,aia-guests=2" as machine parameter in the QEMU
command-line
To test series, we require OpenSBI and Linux with AIA support which can
be found in riscv_aia_v1 branch at:
https://github.com/avpatel/opensbi.git
https://github.com/avpatel/linux.git
This series can be found riscv_aia_v4 branch at:
https://github.com/avpatel/qemu.git
Changes since v3:
- Replaced "aplic,xyz" and "imsic,xyz" DT properties with "riscv,xyz"
DT properties because "aplic" and "imsic" are not valid vendor names
required by Linux DT schema checker.
Changes since v2:
- Update PATCH4 to check and inject interrupt after V=1 when
transitioning from V=0 to V=1
Changes since v1:
- Revamped whole series and created more granular patches
- Added HGEIE and HGEIP CSR emulation for H-extension
- Added APLIC emulation
- Added IMSIC emulation
Anup Patel (22):
target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64
HS-mode
target/riscv: Implement SGEIP bit in hip and hie CSRs
target/riscv: Implement hgeie and hgeip CSRs
target/riscv: Improve delivery of guest external interrupts
target/riscv: Allow setting CPU feature from machine/device emulation
target/riscv: Add AIA cpu feature
target/riscv: Add defines for AIA CSRs
target/riscv: Allow AIA device emulation to set ireg rmw callback
target/riscv: Implement AIA local interrupt priorities
target/riscv: Implement AIA CSRs for 64 local interrupts on RV32
target/riscv: Implement AIA hvictl and hviprioX CSRs
target/riscv: Implement AIA interrupt filtering CSRs
target/riscv: Implement AIA mtopi, stopi, and vstopi CSRs
target/riscv: Implement AIA xiselect and xireg CSRs
target/riscv: Implement AIA IMSIC interface CSRs
hw/riscv: virt: Use AIA INTC compatible string when available
target/riscv: Allow users to force enable AIA CSRs in HART
hw/intc: Add RISC-V AIA APLIC device emulation
hw/riscv: virt: Add optional AIA APLIC support to virt machine
hw/intc: Add RISC-V AIA IMSIC device emulation
hw/riscv: virt: Add optional AIA IMSIC support to virt machine
docs/system: riscv: Document AIA options for virt machine
docs/system/riscv/virt.rst | 16 +
hw/intc/Kconfig | 6 +
hw/intc/meson.build | 2 +
hw/intc/riscv_aplic.c | 970 +++++++++++++++++++++++++
hw/intc/riscv_imsic.c | 443 ++++++++++++
hw/riscv/Kconfig | 2 +
hw/riscv/virt.c | 694 +++++++++++++++---
include/hw/intc/riscv_aplic.h | 73 ++
include/hw/intc/riscv_imsic.h | 68 ++
include/hw/riscv/virt.h | 40 +-
target/riscv/cpu.c | 97 ++-
target/riscv/cpu.h | 67 +-
target/riscv/cpu_bits.h | 132 ++++
target/riscv/cpu_helper.c | 300 +++++++-
target/riscv/csr.c | 1273 ++++++++++++++++++++++++++++++---
target/riscv/machine.c | 24 +-
16 files changed, 3901 insertions(+), 306 deletions(-)
create mode 100644 hw/intc/riscv_aplic.c
create mode 100644 hw/intc/riscv_imsic.c
create mode 100644 include/hw/intc/riscv_aplic.h
create mode 100644 include/hw/intc/riscv_imsic.h
--
2.25.1
- [PATCH v4 00/22] QEMU RISC-V AIA support,
Anup Patel <=
- [PATCH v4 01/22] target/riscv: Fix trap cause for RV32 HS-mode CSR access from RV64 HS-mode, Anup Patel, 2021/10/26
- [PATCH v4 05/22] target/riscv: Allow setting CPU feature from machine/device emulation, Anup Patel, 2021/10/26
- [PATCH v4 03/22] target/riscv: Implement hgeie and hgeip CSRs, Anup Patel, 2021/10/26
- [PATCH v4 06/22] target/riscv: Add AIA cpu feature, Anup Patel, 2021/10/26
- [PATCH v4 07/22] target/riscv: Add defines for AIA CSRs, Anup Patel, 2021/10/26
- [PATCH v4 04/22] target/riscv: Improve delivery of guest external interrupts, Anup Patel, 2021/10/26
- [PATCH v4 02/22] target/riscv: Implement SGEIP bit in hip and hie CSRs, Anup Patel, 2021/10/26
- [PATCH v4 08/22] target/riscv: Allow AIA device emulation to set ireg rmw callback, Anup Patel, 2021/10/26
- [PATCH v4 09/22] target/riscv: Implement AIA local interrupt priorities, Anup Patel, 2021/10/26