Re: [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO

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Re: [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add

From:	Richard Henderson
Subject:	Re: [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO
Date:	Mon, 25 Oct 2021 13:09:41 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/25/21 5:28 AM, Frédéric Pétrot wrote:

-    MO_LEQ   = MO_LE | MO_Q,
+    MO_LEQ   = MO_LE | MO_UQ,


Again, I mentioned that this would require renaming as well...

-    MO_BEQ   = MO_BE | MO_Q,
+    MO_BEQ   = MO_BE | MO_UQ,


... and this...

+    MO_TEUQ  = MO_TE | MO_UQ,
      MO_TESW  = MO_TE | MO_SW,
      MO_TESL  = MO_TE | MO_SL,
-    MO_TEQ   = MO_TE | MO_Q,
+    MO_TEQ   = MO_TE | MO_UQ,
+    MO_TESQ  = MO_TE | MO_SQ,
+    MO_TEO   = MO_TE | MO_UO,


... but you only did MO_TEQ to MO_TEUQ.

Please split the renames from the additions.


r~

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[PATCH v4 00/17] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 2021/10/25
- [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers, Philippe Mathieu-Daudé, 2021/10/25
  - Re: [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers, Richard Henderson, 2021/10/25
- [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO, Richard Henderson <=
- [PATCH v4 03/17] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 03/17] target/riscv: additional macros to check instruction support, Richard Henderson, 2021/10/30
- [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Philippe Mathieu-Daudé, 2021/10/25
    - Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Richard Henderson, 2021/10/25
- [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Philippe Mathieu-Daudé, 2021/10/25
  - Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Richard Henderson, 2021/10/25
- [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, Richard Henderson, 2021/10/30

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