Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritm

qemu-riscv

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Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritm

From:	Philippe Mathieu-Daudé
Subject:	Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers
Date:	Mon, 25 Oct 2021 17:51:35 +0200
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.0

On 10/25/21 14:28, Frédéric Pétrot wrote:
> Introduction of a gen_logic function for bitwise logic to implement
> instructions in which not propagation of information occurs between bits and
> use of this function on the bitwise instructions.
> 
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  target/riscv/translate.c                | 27 +++++++++++++++++++++++++
>  target/riscv/insn_trans/trans_rvb.c.inc |  6 +++---
>  target/riscv/insn_trans/trans_rvi.c.inc | 12 +++++------
>  3 files changed, 36 insertions(+), 9 deletions(-)

Typo "arithmetic" in subject.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>

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Re: [PATCH v4 05/17] target/riscv: array for the 64 upper bits of 128-bit registers, (continued)
- [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 01/17] exec/memop: Rename MO_Q definition as MO_UQ and add MO_UO, Richard Henderson, 2021/10/25
- [PATCH v4 03/17] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 03/17] target/riscv: additional macros to check instruction support, Richard Henderson, 2021/10/30
- [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Philippe Mathieu-Daudé, 2021/10/25
    - Re: [PATCH v4 02/17] qemu/int128: addition of a few 128-bit operations, Richard Henderson, 2021/10/25
- [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Philippe Mathieu-Daudé <=
  - Re: [PATCH v4 04/17] target/riscv: separation of bitwise logic and aritmetic helpers, Richard Henderson, 2021/10/25
- [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 09/17] target/riscv: support for 128-bit bitwise instructions, Richard Henderson, 2021/10/30
- [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 08/17] target/riscv: accessors to registers upper part and 128-bit load/store, Richard Henderson, 2021/10/30
- [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 06/17] target/riscv: setup everything so that riscv128-softmmu compiles, Richard Henderson, 2021/10/30
- [PATCH v4 07/17] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/25
  - Re: [PATCH v4 07/17] target/riscv: moving some insns close to similar insns, Philippe Mathieu-Daudé, 2021/10/25
- [PATCH v4 10/17] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/10/25

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