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Re: [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bi


From: Alistair Francis
Subject: Re: [PATCH v8 65/78] target/riscv: rvv-1.0: relax RV_VLEN_MAX to 1024-bits
Date: Mon, 25 Oct 2021 16:43:22 +1000

On Fri, Oct 15, 2021 at 6:43 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
> --
> ---
>  target/riscv/cpu.h                      | 2 +-
>  target/riscv/insn_trans/trans_rvv.c.inc | 4 ++--
>  target/riscv/vector_helper.c            | 2 +-
>  3 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index 9b2af4e4d0e..49eece111e2 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -101,7 +101,7 @@ typedef struct CPURISCVState CPURISCVState;
>  #include "pmp.h"
>  #endif
>
> -#define RV_VLEN_MAX 256
> +#define RV_VLEN_MAX 1024
>
>  FIELD(VTYPE, VLMUL, 0, 3)
>  FIELD(VTYPE, VSEW, 3, 3)
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc 
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 92a23b52e49..dcb96c954ec 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -567,8 +567,8 @@ static bool ldst_us_trans(uint32_t vd, uint32_t rs1, 
> uint32_t data,
>      base = get_gpr(s, rs1, EXT_NONE);
>
>      /*
> -     * As simd_desc supports at most 256 bytes, and in this implementation,
> -     * the max vector group length is 2048 bytes. So split it into two parts.
> +     * As simd_desc supports at most 2048 bytes, and in this implementation,
> +     * the max vector group length is 4096 bytes. So split it into two parts.
>       *
>       * The first part is vlen in bytes, encoded in maxsz of simd_desc.
>       * The second part is lmul, encoded in data of simd_desc.
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 37b2451bd05..70ddc55e16b 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -124,7 +124,7 @@ static inline int32_t vext_lmul(uint32_t desc)
>  static inline uint32_t vext_max_elems(uint32_t desc, uint32_t esz)
>  {
>      /*
> -     * As simd_desc support at most 256 bytes, the max vlen is 256 bits.
> +     * As simd_desc support at most 2048 bytes, the max vlen is 1024 bits.
>       * so vlen in bytes (vlenb) is encoded as maxsz.
>       */
>      uint32_t vlenb = simd_maxsz(desc);
> --
> 2.25.1
>
>



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