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Re: [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtr
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow |
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Date: |
Mon, 25 Oct 2021 16:08:36 +1000 |
On Fri, Oct 15, 2021 at 6:26 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> * Only do carry-in or borrow-in if is masked (vm=0).
> * Remove clear function from helper functions as the tail elements
> are unchanged in RVV 1.0.
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 20 ++++++++++----------
> target/riscv/insn_trans/trans_rvv.c.inc | 2 +-
> target/riscv/vector_helper.c | 21 ++++++---------------
> 3 files changed, 17 insertions(+), 26 deletions(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index f83c8daf24e..9c4089d7a7b 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -378,16 +378,16 @@ vwsubu_wv 110110 . ..... ..... 010 ..... 1010111
> @r_vm
> vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
> vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
> vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
> -vadc_vvm 010000 1 ..... ..... 000 ..... 1010111 @r_vm_1
> -vadc_vxm 010000 1 ..... ..... 100 ..... 1010111 @r_vm_1
> -vadc_vim 010000 1 ..... ..... 011 ..... 1010111 @r_vm_1
> -vmadc_vvm 010001 1 ..... ..... 000 ..... 1010111 @r_vm_1
> -vmadc_vxm 010001 1 ..... ..... 100 ..... 1010111 @r_vm_1
> -vmadc_vim 010001 1 ..... ..... 011 ..... 1010111 @r_vm_1
> -vsbc_vvm 010010 1 ..... ..... 000 ..... 1010111 @r_vm_1
> -vsbc_vxm 010010 1 ..... ..... 100 ..... 1010111 @r_vm_1
> -vmsbc_vvm 010011 1 ..... ..... 000 ..... 1010111 @r_vm_1
> -vmsbc_vxm 010011 1 ..... ..... 100 ..... 1010111 @r_vm_1
> +vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
> +vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
> +vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
> +vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm
> +vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm
> +vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm
> +vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
> +vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
> +vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm
> +vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm
> vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
> vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
> vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
> b/target/riscv/insn_trans/trans_rvv.c.inc
> index 1fcde9f4df4..f3003d023e5 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1547,7 +1547,7 @@ static bool trans_##NAME(DisasContext *s, arg_rmrr *a)
> \
>
> /*
> * For vadc and vsbc, an illegal instruction exception is raised if the
> - * destination vector register is v0 and LMUL > 1. (Section 12.3)
> + * destination vector register is v0 and LMUL > 1. (Section 12.4)
> */
> static bool opivv_vadc_check(DisasContext *s, arg_rmrr *a)
> {
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 6891f28116f..54405d898b9 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -944,7 +944,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
> *vs2, \
> for (i = 0; i < vl; i++) { \
> ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
> ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
> - uint8_t carry = vext_elem_mask(v0, i); \
> + ETYPE carry = vext_elem_mask(v0, i); \
> \
> *((ETYPE *)vd + H(i)) = DO_OP(s2, s1, carry); \
> } \
> @@ -969,7 +969,7 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong s1,
> void *vs2, \
> \
> for (i = 0; i < vl; i++) { \
> ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
> - uint8_t carry = vext_elem_mask(v0, i); \
> + ETYPE carry = vext_elem_mask(v0, i); \
> \
> *((ETYPE *)vd + H(i)) = DO_OP(s2, (ETYPE)(target_long)s1, carry);\
> } \
> @@ -994,20 +994,15 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void
> *vs2, \
> CPURISCVState *env, uint32_t desc) \
> { \
> uint32_t vl = env->vl; \
> - uint32_t vlmax = vext_max_elems(desc, \
> - ctzl(sizeof(ETYPE))); \
> + uint32_t vm = vext_vm(desc); \
> uint32_t i; \
> \
> for (i = 0; i < vl; i++) { \
> ETYPE s1 = *((ETYPE *)vs1 + H(i)); \
> ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
> - uint8_t carry = vext_elem_mask(v0, i); \
> - \
> + ETYPE carry = !vm && vext_elem_mask(v0, i); \
> vext_set_elem_mask(vd, i, DO_OP(s2, s1, carry)); \
> } \
> - for (; i < vlmax; i++) { \
> - vext_set_elem_mask(vd, i, 0); \
> - } \
> }
>
> GEN_VEXT_VMADC_VVM(vmadc_vvm_b, uint8_t, H1, DO_MADC)
> @@ -1025,19 +1020,15 @@ void HELPER(NAME)(void *vd, void *v0, target_ulong
> s1, \
> void *vs2, CPURISCVState *env, uint32_t desc) \
> { \
> uint32_t vl = env->vl; \
> - uint32_t vlmax = vext_max_elems(desc, ctzl(sizeof(ETYPE))); \
> + uint32_t vm = vext_vm(desc); \
> uint32_t i; \
> \
> for (i = 0; i < vl; i++) { \
> ETYPE s2 = *((ETYPE *)vs2 + H(i)); \
> - uint8_t carry = vext_elem_mask(v0, i); \
> - \
> + ETYPE carry = !vm && vext_elem_mask(v0, i); \
> vext_set_elem_mask(vd, i, \
> DO_OP(s2, (ETYPE)(target_long)s1, carry)); \
> } \
> - for (; i < vlmax; i++) { \
> - vext_set_elem_mask(vd, i, 0); \
> - } \
> }
>
> GEN_VEXT_VMADC_VXM(vmadc_vxm_b, uint8_t, H1, DO_MADC)
> --
> 2.25.1
>
>
- Re: [PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions, (continued)
- [PATCH v8 37/78] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2021/10/15
- [PATCH v8 39/78] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/10/15
- [PATCH v8 40/78] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/10/15
- [PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/10/15
- [PATCH v8 41/78] target/riscv: rvv-1.0: single-width averaging add and subtract instructions, frank . chang, 2021/10/15
- [PATCH v8 42/78] target/riscv: rvv-1.0: single-width bit shift instructions, frank . chang, 2021/10/15
- [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow, frank . chang, 2021/10/15
- Re: [PATCH v8 43/78] target/riscv: rvv-1.0: integer add-with-carry/subtract-with-borrow,
Alistair Francis <=
- [PATCH v8 44/78] target/riscv: rvv-1.0: narrowing integer right shift instructions, frank . chang, 2021/10/15
- [PATCH v8 45/78] target/riscv: rvv-1.0: widening integer multiply-add instructions, frank . chang, 2021/10/15
- [PATCH v8 46/78] target/riscv: rvv-1.0: single-width saturating add and subtract instructions, frank . chang, 2021/10/15
- [PATCH v8 47/78] target/riscv: rvv-1.0: integer comparison instructions, frank . chang, 2021/10/15
- [PATCH v8 48/78] target/riscv: rvv-1.0: floating-point compare instructions, frank . chang, 2021/10/15
- [PATCH v8 49/78] target/riscv: rvv-1.0: mask-register logical instructions, frank . chang, 2021/10/15
- [PATCH v8 50/78] target/riscv: rvv-1.0: slide instructions, frank . chang, 2021/10/15
- [PATCH v8 51/78] target/riscv: rvv-1.0: floating-point slide instructions, frank . chang, 2021/10/15
- [PATCH v8 52/78] target/riscv: rvv-1.0: narrowing fixed-point clip instructions, frank . chang, 2021/10/15