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Re: [PATCH v3 13/21] target/riscv: support for 128-bit shift instruction
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From: |
Frédéric Pétrot |
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Subject: |
Re: [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions |
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Date: |
Mon, 25 Oct 2021 00:49:01 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 |
Le 20/10/2021 à 21:06, Richard Henderson a écrit :
> On 10/19/21 2:48 AM, Frédéric Pétrot wrote:
>
> Hmm. 3 * (and + shift + cmp + cmov) + 2 * (sub + or) = 16 ops.
> Not horrible...
>
> Let's see.
>
> ls = sh & 63; 1
> rs = -sh & 63; 3
> hs = sh & 64; 4
>
> ll = s1l << ls; 5
> h0 = s1h << ls; 6
> lr = s1l >> rs; 7
> h1 = h0 | lr; 8
>
> dl = hs ? 0 : ll; 10
> dh = hs ? ll : h1; 12
>
> That seems right, and would be 4 ops smaller.
> Would need testing of course.
Nice !
The case when sh is 0 is specific, so we need an additional
cmov, but this is still 3 ops better.
Frédéric
>
>
> r~
--
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
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- Re: [PATCH v3 10/21] target/riscv: support for 128-bit loads and store, (continued)
- [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/10/19
- [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/19
- [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/10/19
- [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/19
- [PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/10/19
- [PATCH v3 21/21] target/riscv: support for 128-bit satp, Frédéric Pétrot, 2021/10/19
- [PATCH v3 15/21] target/riscv: support for 128-bit M extension, Frédéric Pétrot, 2021/10/19
- [PATCH v3 18/21] target/riscv: modification of the trans_csrxx for 128-bit support, Frédéric Pétrot, 2021/10/19
- [PATCH v3 16/21] target/riscv: adding high part of some csrs, Frédéric Pétrot, 2021/10/19