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Re: [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bi
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From: |
Frédéric Pétrot |
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Subject: |
Re: [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers |
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Date: |
Fri, 22 Oct 2021 08:06:09 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 |
Le 20/10/2021 à 16:44, Richard Henderson a écrit :
> On 10/19/21 2:47 AM, Frédéric Pétrot wrote:
>> The upper 64-bit of the 128-bit registers have now a place inside
>> the cpu state structure, and are created as globals for future use.
>>
>> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
>> Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
>> ---
>> target/riscv/translate.c | 5 ++++-
>> 2 files changed, 5 insertions(+), 1 deletion(-)
>> for (i = 1; i < 32; i++) {
>> cpu_gpr[i] = tcg_global_mem_new(cpu_env,
>> offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]);
>> + cpu_gprh[i] = tcg_global_mem_new(cpu_env,
>> + offsetof(CPURISCVState, gprh[i]), riscv_int_regnames[i]);
>
> This will just be confusing in the tcg dumps -- let's not name the two temps
> the
> identically.
Agreed.
> Honestly, I'm not 100% thrilled about the / that appears in the current name;
> I
> think it would be easiest to do
>
> g_string_printf("x%d", i)
> and
> g_string_printf("x%dh", i)
Registers sw names are used by gcc -S and the default objdump -d output,
and also by disas/riscv.c, so dropping them might be a bit rough.
For now I'll just add an h in the existing names, and suggest we wait to see
if anyone cares.
Frédéric
--
+---------------------------------------------------------------------------+
| Frédéric Pétrot, Pr. Grenoble INP-Ensimag/TIMA, Ensimag deputy director |
| Mob/Pho: +33 6 74 57 99 65/+33 4 76 57 48 70 Ad augusta per angusta |
| http://tima.univ-grenoble-alpes.fr frederic.petrot@univ-grenoble-alpes.fr |
+---------------------------------------------------------------------------+
- [PATCH v3 00/21] Adding partial support for 128-bit riscv target, Frédéric Pétrot, 2021/10/19
- [PATCH v3 02/21] memory: add a few defines for octo (128-bit) values, Frédéric Pétrot, 2021/10/19
- [PATCH v3 04/21] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/19
- [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/19
- [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/19
- [PATCH v3 09/21] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/19
- [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/19
- [PATCH v3 01/21] memory: change define name for consistency, Frédéric Pétrot, 2021/10/19
- [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/19
- [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/19