Re: [PATCH v3 09/21] target/riscv: moving some insns close to similar in

qemu-riscv

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Re: [PATCH v3 09/21] target/riscv: moving some insns close to similar in

From:	Richard Henderson
Subject:	Re: [PATCH v3 09/21] target/riscv: moving some insns close to similar insns
Date:	Wed, 20 Oct 2021 08:11:25 -0700
User-agent:	Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0

On 10/19/21 2:48 AM, Frédéric Pétrot wrote:

lwu and ld are functionally close to the other loads, but were after the
stores in the source file.
Similarly, xor was away from or and and by two arithmetic functions, while
the immediate versions were nicely put together.
This patch moves the aforementioned loads after lhu, and xor above or,
where they more logically belong.

Signed-off-by: Frédéric Pétrot<frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas<fabien.portas@grenoble-inp.org>
---
  target/riscv/insn_trans/trans_rvi.c.inc | 34 ++++++++++++-------------
  1 file changed, 17 insertions(+), 17 deletions(-)


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~

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Re: [PATCH v3 02/21] memory: add a few defines for octo (128-bit) values, (continued)
- [PATCH v3 04/21] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 04/21] target/riscv: additional macros to check instruction support, Richard Henderson, 2021/10/20
    - Re: [PATCH v3 04/21] target/riscv: additional macros to check instruction support, Frédéric Pétrot, 2021/10/21
- [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations, Richard Henderson, 2021/10/19
- [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers, Richard Henderson, 2021/10/20
    - Re: [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/22
- [PATCH v3 09/21] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 09/21] target/riscv: moving some insns close to similar insns, Richard Henderson <=
- [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, Richard Henderson, 2021/10/20
- [PATCH v3 01/21] memory: change define name for consistency, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 01/21] memory: change define name for consistency, Philippe Mathieu-Daudé, 2021/10/20
- [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part, Richard Henderson, 2021/10/20
- [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles, Richard Henderson, 2021/10/20
- [PATCH v3 10/21] target/riscv: support for 128-bit loads and store, Frédéric Pétrot, 2021/10/19
  - Re: [PATCH v3 10/21] target/riscv: support for 128-bit loads and store, Richard Henderson, 2021/10/20

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