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Re: [PATCH v3 01/21] memory: change define name for consistency
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From: |
Philippe Mathieu-Daudé |
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Subject: |
Re: [PATCH v3 01/21] memory: change define name for consistency |
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Date: |
Wed, 20 Oct 2021 17:07:50 +0200 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.1.0 |
On 10/19/21 11:47, Frédéric Pétrot wrote:
> Changed MO_Q into MO_UQ so as to avoid confusion, as suggested by
> Philippe Mathieu-Daudé.
>
> Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
> ---
> include/exec/memop.h | 8 ++++----
> target/arm/translate-a32.h | 4 ++--
> target/arm/translate-a64.c | 8 ++++----
> target/arm/translate-neon.c | 6 +++---
> target/arm/translate-sve.c | 2 +-
> target/arm/translate-vfp.c | 8 ++++----
> target/arm/translate.c | 2 +-
> target/ppc/translate.c | 24 +++++++++++-----------
> target/sparc/translate.c | 4 ++--
> target/ppc/translate/fixedpoint-impl.c.inc | 20 +++++++++---------
> target/ppc/translate/fp-impl.c.inc | 4 ++--
> target/ppc/translate/vsx-impl.c.inc | 4 ++--
> tcg/aarch64/tcg-target.c.inc | 2 +-
> tcg/arm/tcg-target.c.inc | 10 ++++-----
> tcg/i386/tcg-target.c.inc | 4 ++--
> tcg/mips/tcg-target.c.inc | 4 ++--
> tcg/ppc/tcg-target.c.inc | 8 ++++----
> tcg/riscv/tcg-target.c.inc | 6 +++---
> tcg/s390x/tcg-target.c.inc | 10 ++++-----
> 19 files changed, 69 insertions(+), 69 deletions(-)
>
> diff --git a/include/exec/memop.h b/include/exec/memop.h
> index 04264ffd6b..c554bb0ee8 100644
> --- a/include/exec/memop.h
> +++ b/include/exec/memop.h
> @@ -88,26 +88,26 @@ typedef enum MemOp {
> MO_SB = MO_SIGN | MO_8,
> MO_SW = MO_SIGN | MO_16,
> MO_SL = MO_SIGN | MO_32,
> - MO_Q = MO_64,
> + MO_UQ = MO_64,
> diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc
> index 633b8a37ba..e31f454695 100644
> --- a/tcg/arm/tcg-target.c.inc
> +++ b/tcg/arm/tcg-target.c.inc
> @@ -1443,13 +1443,13 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
> #ifdef HOST_WORDS_BIGENDIAN
> [MO_UW] = helper_be_lduw_mmu,
> [MO_UL] = helper_be_ldul_mmu,
> - [MO_Q] = helper_be_ldq_mmu,
> + [MO_UQ] = helper_be_ldq_mmu,
> [MO_SW] = helper_be_ldsw_mmu,
> [MO_SL] = helper_be_ldul_mmu,
> #else
> [MO_UW] = helper_le_lduw_mmu,
> [MO_UL] = helper_le_ldul_mmu,
> - [MO_Q] = helper_le_ldq_mmu,
> + [MO_UQ] = helper_le_ldq_mmu,
> [MO_SW] = helper_le_ldsw_mmu,
> [MO_SL] = helper_le_ldul_mmu,
> #endif
> --- a/tcg/ppc/tcg-target.c.inc
> +++ b/tcg/ppc/tcg-target.c.inc
> @@ -1935,24 +1935,24 @@ static const uint32_t qemu_ldx_opc[(MO_SSIZE +
> MO_BSWAP) + 1] = {
> [MO_UB] = LBZX,
> [MO_UW] = LHZX,
> [MO_UL] = LWZX,
> - [MO_Q] = LDX,
> + [MO_UQ] = LDX,
> [MO_SW] = LHAX,
> [MO_SL] = LWAX,
> [MO_BSWAP | MO_UB] = LBZX,
> [MO_BSWAP | MO_UW] = LHBRX,
> [MO_BSWAP | MO_UL] = LWBRX,
> - [MO_BSWAP | MO_Q] = LDBRX,
> + [MO_BSWAP | MO_UQ] = LDBRX,
> };
>
> static const uint32_t qemu_stx_opc[(MO_SIZE + MO_BSWAP) + 1] = {
> [MO_UB] = STBX,
> [MO_UW] = STHX,
> [MO_UL] = STWX,
> - [MO_Q] = STDX,
> + [MO_UQ] = STDX,
> [MO_BSWAP | MO_UB] = STBX,
> [MO_BSWAP | MO_UW] = STHBRX,
> [MO_BSWAP | MO_UL] = STWBRX,
> - [MO_BSWAP | MO_Q] = STDBRX,
> + [MO_BSWAP | MO_UQ] = STDBRX,
> };
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 9b13a46fb4..b621694321 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -862,7 +862,7 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
> #if TCG_TARGET_REG_BITS == 64
> [MO_SL] = helper_be_ldsl_mmu,
> #endif
> - [MO_Q] = helper_be_ldq_mmu,
> + [MO_UQ] = helper_be_ldq_mmu,
> #else
> [MO_UW] = helper_le_lduw_mmu,
> [MO_SW] = helper_le_ldsw_mmu,
> @@ -870,7 +870,7 @@ static void * const qemu_ld_helpers[MO_SSIZE + 1] = {
> #if TCG_TARGET_REG_BITS == 64
> [MO_SL] = helper_le_ldsl_mmu,
> #endif
> - [MO_Q] = helper_le_ldq_mmu,
> + [MO_UQ] = helper_le_ldq_mmu,
> #endif
> };
Some '=' are now mis-indented.
Otherwise:
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Also this subject would be more appropriate:
"exec/memop: Rename MO_Q definition as MO_UQ"
Regards,
Phil.
- [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations, (continued)
- [PATCH v3 03/21] Int128.h: addition of a few 128-bit operations, Frédéric Pétrot, 2021/10/19
- [PATCH v3 06/21] target/riscv: array for the 64 upper bits of 128-bit registers, Frédéric Pétrot, 2021/10/19
- [PATCH v3 09/21] target/riscv: moving some insns close to similar insns, Frédéric Pétrot, 2021/10/19
- [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/19
- [PATCH v3 01/21] memory: change define name for consistency, Frédéric Pétrot, 2021/10/19
- Re: [PATCH v3 01/21] memory: change define name for consistency,
Philippe Mathieu-Daudé <=
- [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/19
- [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/19
- [PATCH v3 10/21] target/riscv: support for 128-bit loads and store, Frédéric Pétrot, 2021/10/19
- [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions, Frédéric Pétrot, 2021/10/19
- [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/19