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[PATCH v6 11/15] target/riscv: Adjust trans_rev8_32 for riscv64
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From: |
Richard Henderson |
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Subject: |
[PATCH v6 11/15] target/riscv: Adjust trans_rev8_32 for riscv64 |
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Date: |
Tue, 19 Oct 2021 20:17:05 -0700 |
When target_long is 64-bit, we still want a 32-bit bswap for rev8.
Since this opcode is specific to RV32, we need not conditionalize.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/riscv/insn_trans/trans_rvb.c.inc | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc
b/target/riscv/insn_trans/trans_rvb.c.inc
index 9ef8ab94ad..d6f9e9fc83 100644
--- a/target/riscv/insn_trans/trans_rvb.c.inc
+++ b/target/riscv/insn_trans/trans_rvb.c.inc
@@ -232,11 +232,16 @@ static bool trans_rol(DisasContext *ctx, arg_rol *a)
return gen_shift(ctx, a, EXT_NONE, tcg_gen_rotl_tl);
}
+static void gen_rev8_32(TCGv ret, TCGv src1)
+{
+ tcg_gen_bswap32_tl(ret, src1, TCG_BSWAP_OS);
+}
+
static bool trans_rev8_32(DisasContext *ctx, arg_rev8_32 *a)
{
REQUIRE_32BIT(ctx);
REQUIRE_ZBB(ctx);
- return gen_unary(ctx, a, EXT_NONE, tcg_gen_bswap_tl);
+ return gen_unary(ctx, a, EXT_NONE, gen_rev8_32);
}
static bool trans_rev8_64(DisasContext *ctx, arg_rev8_64 *a)
--
2.25.1
- [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length, Richard Henderson, 2021/10/19
- [PATCH v6 01/15] target/riscv: Move cpu_get_tb_cpu_state out of line, Richard Henderson, 2021/10/19
- [PATCH v6 02/15] target/riscv: Create RISCVMXL enumeration, Richard Henderson, 2021/10/19
- [PATCH v6 08/15] target/riscv: Replace is_32bit with get_xl/get_xlen, Richard Henderson, 2021/10/19
- [PATCH v6 07/15] target/riscv: Properly check SEW in amo_op, Richard Henderson, 2021/10/19
- [PATCH v6 04/15] target/riscv: Replace riscv_cpu_is_32bit with riscv_cpu_mxl, Richard Henderson, 2021/10/19
- [PATCH v6 06/15] target/riscv: Use REQUIRE_64BIT in amo_check64, Richard Henderson, 2021/10/19
- [PATCH v6 09/15] target/riscv: Replace DisasContext.w with DisasContext.ol, Richard Henderson, 2021/10/19
- [PATCH v6 10/15] target/riscv: Use gen_arith_per_ol for RVM, Richard Henderson, 2021/10/19
- [PATCH v6 03/15] target/riscv: Split misa.mxl and misa.ext, Richard Henderson, 2021/10/19
- [PATCH v6 11/15] target/riscv: Adjust trans_rev8_32 for riscv64,
Richard Henderson <=
- [PATCH v6 05/15] target/riscv: Add MXL/SXL/UXL to TB_FLAGS, Richard Henderson, 2021/10/19
- [PATCH v6 12/15] target/riscv: Use gen_unary_per_ol for RVB, Richard Henderson, 2021/10/19
- [PATCH v6 14/15] target/riscv: Use riscv_csrrw_debug for cpu_dump, Richard Henderson, 2021/10/19
- [PATCH v6 13/15] target/riscv: Use gen_shift*_per_ol for RVB, RVI, Richard Henderson, 2021/10/19
- [PATCH v6 15/15] target/riscv: Compute mstatus.sd on demand, Richard Henderson, 2021/10/19
- Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length, Alistair Francis, 2021/10/20
- Re: [PATCH v6 00/15] target/riscv: Rationalize XLEN and operand length, LIU Zhiwei, 2021/10/22