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[PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions
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From: |
Frédéric Pétrot |
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Subject: |
[PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions |
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Date: |
Tue, 19 Oct 2021 11:48:03 +0200 |
Adding the 128-bit version of lui and auipc.
Signed-off-by: Frédéric Pétrot <frederic.petrot@univ-grenoble-alpes.fr>
Co-authored-by: Fabien Portas <fabien.portas@grenoble-inp.org>
---
target/riscv/insn_trans/trans_rvi.c.inc | 19 +++++++++++++++++--
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvi.c.inc
b/target/riscv/insn_trans/trans_rvi.c.inc
index 92f41f3a86..b5e292a2aa 100644
--- a/target/riscv/insn_trans/trans_rvi.c.inc
+++ b/target/riscv/insn_trans/trans_rvi.c.inc
@@ -26,14 +26,17 @@ static bool trans_illegal(DisasContext *ctx, arg_empty *a)
static bool trans_c64_illegal(DisasContext *ctx, arg_empty *a)
{
- REQUIRE_64BIT(ctx);
- return trans_illegal(ctx, a);
+ REQUIRE_64_OR_128BIT(ctx);
+ return trans_illegal(ctx, a);
}
static bool trans_lui(DisasContext *ctx, arg_lui *a)
{
if (a->rd != 0) {
tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm);
+ if (get_xl_max(ctx) == MXL_RV128) {
+ tcg_gen_movi_tl(cpu_gprh[a->rd], -(a->imm < 0));
+ }
}
return true;
}
@@ -41,7 +44,19 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
if (a->rd != 0) {
+ if (get_xl_max(ctx) == MXL_RV128) {
+ /* TODO : when pc is 128 bits, use all its bits */
+ TCGv pc = tcg_constant_tl(ctx->base.pc_next),
+ imml = tcg_constant_tl(a->imm),
+ immh = tcg_constant_tl(-(a->imm < 0)),
+ zero = tcg_constant_tl(0);
+ tcg_gen_add2_tl(cpu_gpr[a->rd], cpu_gprh[a->rd],
+ pc, zero,
+ imml, immh);
+ return true;
+ }
tcg_gen_movi_tl(cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
+ return true;
}
return true;
}
--
2.33.0
- [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, (continued)
- [PATCH v3 05/21] target/riscv: separation of bitwise logic and aritmetic helpers, Frédéric Pétrot, 2021/10/19
- [PATCH v3 01/21] memory: change define name for consistency, Frédéric Pétrot, 2021/10/19
- [PATCH v3 08/21] target/riscv: adding accessors to the registers upper part, Frédéric Pétrot, 2021/10/19
- [PATCH v3 07/21] target/riscv: setup everything so that riscv128-softmmu compiles, Frédéric Pétrot, 2021/10/19
- [PATCH v3 10/21] target/riscv: support for 128-bit loads and store, Frédéric Pétrot, 2021/10/19
- [PATCH v3 12/21] target/riscv: support for 128-bit U-type instructions,
Frédéric Pétrot <=
- [PATCH v3 11/21] target/riscv: support for 128-bit bitwise instructions, Frédéric Pétrot, 2021/10/19
- [PATCH v3 14/21] target/riscv: support for 128-bit arithmetic instructions, Frédéric Pétrot, 2021/10/19
- [PATCH v3 13/21] target/riscv: support for 128-bit shift instructions, Frédéric Pétrot, 2021/10/19
- [PATCH v3 17/21] target/riscv: helper functions to wrap calls to 128-bit csr insns, Frédéric Pétrot, 2021/10/19