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Re: [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction
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From: |
Alistair Francis |
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Subject: |
Re: [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction |
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Date: |
Mon, 18 Oct 2021 15:54:04 +1000 |
On Fri, Oct 15, 2021 at 6:08 PM <frank.chang@sifive.com> wrote:
>
> From: Frank Chang <frank.chang@sifive.com>
>
> Signed-off-by: Frank Chang <frank.chang@sifive.com>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/insn32.decode | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
> index 3ac5162aeb7..ab274dcde12 100644
> --- a/target/riscv/insn32.decode
> +++ b/target/riscv/insn32.decode
> @@ -633,7 +633,7 @@ vmsbf_m 010100 . ..... 00001 010 ..... 1010111
> @r2_vm
> vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
> vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
> viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
> -vid_v 010110 . 00000 10001 010 ..... 1010111 @r1_vm
> +vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
> vext_x_v 001100 1 ..... ..... 010 ..... 1010111 @r
> vmv_s_x 001101 1 00000 ..... 110 ..... 1010111 @r2
> vfmv_f_s 001100 1 ..... 00000 001 ..... 1010111 @r2rd
> --
> 2.25.1
>
>
- [PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction, (continued)
- [PATCH v8 29/78] target/riscv: rvv-1.0: count population in mask instruction, frank . chang, 2021/10/15
- [PATCH 29/76] target/riscv: rvv-1.0: mask population count instruction, frank . chang, 2021/10/15
- [PATCH v8 30/78] target/riscv: rvv-1.0: find-first-set mask bit instruction, frank . chang, 2021/10/15
- [PATCH v8 31/78] target/riscv: rvv-1.0: set-X-first mask bit instructions, frank . chang, 2021/10/15
- [PATCH v8 32/78] target/riscv: rvv-1.0: iota instruction, frank . chang, 2021/10/15
- [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction, frank . chang, 2021/10/15
- Re: [PATCH v8 33/78] target/riscv: rvv-1.0: element index instruction,
Alistair Francis <=
- [PATCH v8 34/78] target/riscv: rvv-1.0: allow load element with sign-extended, frank . chang, 2021/10/15
- [PATCH v8 35/78] target/riscv: rvv-1.0: register gather instructions, frank . chang, 2021/10/15
- [PATCH v8 36/78] target/riscv: rvv-1.0: integer scalar move instructions, frank . chang, 2021/10/15
- [PATCH v8 37/78] target/riscv: rvv-1.0: floating-point move instruction, frank . chang, 2021/10/15
- [PATCH v8 39/78] target/riscv: rvv-1.0: whole register move instructions, frank . chang, 2021/10/15
- [PATCH v8 40/78] target/riscv: rvv-1.0: integer extension instructions, frank . chang, 2021/10/15
- [PATCH v8 38/78] target/riscv: rvv-1.0: floating-point scalar move instructions, frank . chang, 2021/10/15